Hi Michael,

 

     So sorry for the long response. We didn’t encounter this issue on our side with APL and KBL NUC. Could you share the environment on your side, and how to reproduce this issue?

 

Thanks,

Chenglei

 

From: Marathe, Yogesh
Sent: Monday, October 8, 2018 3:45 PM
To: Michael Goffioul <michael.goffioul@gmail.com>; Tan, Ming <ming.tan@intel.com>; Ren, Chenglei <chenglei.ren@intel.com>
Cc: celadon@lists.01.org
Subject: RE: [01.org Celadon] Boot failure

 

+Chenglei.

 

From: Celadon [mailto:celadon-bounces@lists.01.org] On Behalf Of Michael Goffioul
Sent: Tuesday, October 2, 2018 12:10 AM
To: Tan, Ming <ming.tan@intel.com>
Cc: celadon@lists.01.org
Subject: Re: [01.org Celadon] Boot failure

 

On Wed, Sep 26, 2018 at 9:30 PM Michael Goffioul <michael.goffioul@gmail.com> wrote:

  For the display issue, @Arun, can you let some display engineer to help it?

 

Not sure this is relevant, but I've added "drm.debug=0x1e log_buf_len=1M" to the kernel command line and when the problem occurs I'm seeing a difference in the dmesg output. I've copied the logs when I noticed the change (before and after):

 

[ 1087.562915] [drm:drm_atomic_state_init] Allocated atomic state ffffa1f7c6a61000

[ 1087.562934] [drm:drm_atomic_get_plane_state] Added [PLANE:28:primary A] ffffa1f7d2b49f00 state to ffffa1f7c6a61000

[ 1087.562944] [drm:drm_atomic_get_crtc_state] Added [CRTC:40:pipe A] ffffa1f835bfa000 state to ffffa1f7c6a61000

[ 1087.562950] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa1f7d2b49f00 to [CRTC:40:pipe A]

[ 1087.562957] [drm:drm_atomic_set_fb_for_plane] Set [FB:75] for plane state ffffa1f7d2b49f00

[ 1087.562969] [drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite A] ffffa1f82947a600 state to ffffa1f7c6a61000

[ 1087.562974] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa1f82947a600 to [CRTC:40:pipe A]

[ 1087.562979] [drm:drm_atomic_set_fb_for_plane] Set [FB:79] for plane state ffffa1f82947a600

[ 1087.563002] [drm:drm_atomic_check_only] checking ffffa1f7c6a61000

[ 1087.563020] [drm:intel_plane_atomic_calc_changes] [CRTC:40:pipe A] has [PLANE:28:primary A] with fb 75

[ 1087.563024] [drm:intel_plane_atomic_calc_changes] [PLANE:28:primary A] visible 1 -> 1, off 0, on 0, ms 0

[ 1087.563032] [drm:intel_plane_atomic_calc_changes] [CRTC:40:pipe A] has [PLANE:31:sprite A] with fb 79

[ 1087.563037] [drm:intel_plane_atomic_calc_changes] [PLANE:31:sprite A] visible 1 -> 1, off 0, on 0, ms 0

[ 1087.563046] [drm:drm_atomic_nonblocking_commit] committing ffffa1f7c6a61000 nonblocking

[ 1087.572114] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa1f7c6a61000

[ 1087.572125] [drm:__drm_atomic_state_free] Freeing atomic state ffffa1f7c6a61000

[ 1087.579276] [drm:drm_mode_addfb2] [FB:76]

[ 1087.579356] [drm:drm_mode_addfb2] [FB:81]

[ 1087.579389] [drm:drm_atomic_state_init] Allocated atomic state ffffa1f833e34800

[ 1087.579402] [drm:drm_atomic_get_plane_state] Added [PLANE:28:primary A] ffffa1f7d2bcc400 state to ffffa1f833e34800

[ 1087.579409] [drm:drm_atomic_get_crtc_state] Added [CRTC:40:pipe A] ffffa1f7e2916800 state to ffffa1f833e34800

[ 1087.579415] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa1f7d2bcc400 to [CRTC:40:pipe A]

[ 1087.579420] [drm:drm_atomic_set_fb_for_plane] Set [FB:81] for plane state ffffa1f7d2bcc400

[ 1087.579431] [drm:drm_atomic_get_plane_state] Added [PLANE:31:sprite A] ffffa1f80cbdf000 state to ffffa1f833e34800

[ 1087.579436] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa1f80cbdf000 to [CRTC:40:pipe A]

[ 1087.579442] [drm:drm_atomic_set_fb_for_plane] Set [FB:70] for plane state ffffa1f80cbdf000

[ 1087.579448] [drm:drm_atomic_check_only] checking ffffa1f833e34800

[ 1087.579454] [drm:drm_atomic_check_only] Invalid pixel format AB24 little-endian (0x34324241)

[ 1087.579458] [drm:drm_atomic_check_only] [PLANE:28:primary A] atomic core check failed

[ 1087.579464] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa1f833e34800

[ 1087.579470] [drm:__drm_atomic_state_free] Freeing atomic state ffffa1f833e34800

 

What caught my attention is the line "Invalid pixel format AB24 little-endian (0x34324241)". Looking at the code for drm_plane_check_pixel_format, the log line is consistent with the -22 (-EINVAL) error returned to the hwcomposer.

 

Any feedback on the above?

Is the pixel format used by hwcomposer not compatible with by chipset?

If not, how is it possible that the graphics stack starts fine, but problem only occur during transition?

Is there a workaround for it?

 

Thanks,

Michael.