12:20 a.m.
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Hi,
I have been working on some new i915 uAPI proposals which sounds interesting
for the intel-vaapi-driver project.
Primarily this is about changing the way VCS engines are selected at execbuf
time, adding the i915 feature to load-balance those batches, and allowing
userspace to opt-in to such behaviour.
You can find this patches here:
https://patchwork.freedesktop.org/series/33706/
This series contains proof of concept patches against intel-vaapi-driver to make
use of these proposed i915 features.
I am not familiar of the code base so there might be smaller or bigger mistakes
here, please be aware.
But in essence the code seems to pass the test shipped with the project and is
also able to utilize the features as intended when run for instance from ffmpeg:
root@sc:~/ffmpeg# VA_INTEL_CONCURRENT=0 perf stat -a -e i915/vcs0-busy/,i915/vcs1-busy/
ffmpeg -loglevel panic -hwaccel vaapi -hwaccel_output_format vaapi -i
~/bbb_sunflower_1080p_60fps_normal.mp4 -f null -
Performance counter stats for 'system wide':
57,568,097,358 ns i915/vcs0-busy/
0 ns i915/vcs1-busy/
57.585753514 seconds time elapsed
root@sc:~/ffmpeg# VA_INTEL_CONCURRENT=1 perf stat -a -e i915/vcs0-busy/,i915/vcs1-busy/
ffmpeg -loglevel panic -hwaccel vaapi -hwaccel_output_format vaapi -i
~/bbb_sunflower_1080p_60fps_normal.mp4 -f null -
Performance counter stats for 'system wide':
29,152,427,164 ns i915/vcs0-busy/
29,115,272,714 ns i915/vcs1-busy/
40.733992298 seconds time elapsed
This shows that decoding a single stream on a SKL GT4 part it is able to
utilize both VCS engines for a nice performance improvement.
It could also have a beneficial effect when multiple parallel streams are
decoded or encoded, but in this case it will depend on the exact streams.
Because the current i915 RFC does a trivial round-robin engine balancing only.
In the future we may decide to take the route of making the i915 scheduler
smarter in this respect.
Main question is whether you guys can see some flaws in this approach, both
design and implementation, and whether you would be interested in having such
extensions in your code base?
Tvrtko Ursulin (9):
Create a dedicated context
Mark the context as concurrent
Use engine class when allocating batch buffers
Use class and instance in batch override
Store class/instance in batch and use for flushing
Use class/instance based execbuf
Store engine features in batch
Feature based VCS override
Use engine features for HEVC decode
src/gen6_mfc.c | 6 +-
src/gen6_mfd.c | 3 +-
src/gen75_mfc.c | 6 +-
src/gen75_mfd.c | 3 +-
src/gen75_vpp_gpe.c | 3 +-
src/gen75_vpp_vebox.c | 3 +-
src/gen7_mfd.c | 3 +-
src/gen8_mfc.c | 10 ++-
src/gen8_mfd.c | 5 +-
src/gen9_hevc_encoder.c | 4 +-
src/gen9_mfc_hevc.c | 7 +-
src/gen9_mfd.c | 11 ++-
src/gen9_vdenc.c | 2 +-
src/gen9_vp9_encoder.c | 2 +-
src/i965_avc_encoder.c | 4 +-
src/i965_drv_video.c | 8 ++-
src/i965_encoder.c | 3 +-
src/i965_encoder_vp8.c | 6 +-
src/i965_media.c | 3 +-
src/i965_post_processing.c | 3 +-
src/intel_batchbuffer.c | 176 +++++++++++++++++++++++++--------------------
src/intel_batchbuffer.h | 99 ++++++++++++++++++++-----
src/intel_driver.c | 10 ++-
src/intel_driver.h | 3 +
src/intel_memman.c | 13 +++-
src/intel_memman.h | 2 +-
26 files changed, 264 insertions(+), 134 deletions(-)
--
2.14.1
12:20 a.m.
New subject: [RFC 1/9] Create a dedicated context
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
This will enable turning on a special context feature
in a following patch.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_batchbuffer.c | 7 ++++++-
src/intel_batchbuffer.h | 2 ++
src/intel_driver.h | 1 +
src/intel_memman.c | 4 ++++
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 09a9737d0989..e7d038079e5f 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -99,6 +99,8 @@ intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int
buffer_size
batch->intel = intel;
batch->flag = flag;
batch->run = drm_intel_bo_mrb_exec;
+ if (intel->ctx)
+ batch->run_ctx = drm_intel_gem_bo_context_exec;
if (IS_GEN6(intel->device_info) &&
flag == I915_EXEC_RENDER)
@@ -144,7 +146,10 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch)
batch->ptr += 4;
dri_bo_unmap(batch->buffer);
used = batch->ptr - batch->map;
- batch->run(batch->buffer, used, 0, 0, 0, batch->flag);
+ if (batch->run_ctx)
+ batch->run_ctx(batch->buffer, batch->intel->ctx, used,
batch->flag);
+ else
+ batch->run(batch->buffer, used, 0, 0, 0, batch->flag);
intel_batchbuffer_reset(batch, batch->size);
}
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index cbc5d799f6e6..a4a3ed27fd45 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -23,6 +23,8 @@ struct intel_batchbuffer {
int (*run)(drm_intel_bo *bo, int used,
drm_clip_rect_t *cliprects, int num_cliprects,
int DR4, unsigned int ring_flag);
+ int (*run_ctx)(drm_intel_bo *bo, drm_intel_context *ctx, int used,
+ unsigned int flags);
/* Used for Sandybdrige workaround */
dri_bo *wa_render_bo;
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 80643c32d63e..2999d8ebcfa2 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -181,6 +181,7 @@ struct intel_driver_data {
int locked;
dri_bufmgr *bufmgr;
+ drm_intel_context *ctx;
unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
diff --git a/src/intel_memman.c b/src/intel_memman.c
index ca86991bbb7d..8ff195e50b0f 100644
--- a/src/intel_memman.c
+++ b/src/intel_memman.c
@@ -38,6 +38,8 @@ intel_memman_init(struct intel_driver_data *intel)
assert(intel->bufmgr);
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
+ intel->ctx = drm_intel_gem_context_create(intel->bufmgr);
+
if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_DUMP_AUB) {
drm_intel_bufmgr_gem_set_aub_filename(intel->bufmgr,
"va.aub");
@@ -50,6 +52,8 @@ intel_memman_init(struct intel_driver_data *intel)
Bool
intel_memman_terminate(struct intel_driver_data *intel)
{
+ if (intel->ctx)
+ drm_intel_gem_context_destroy(intel->ctx);
drm_intel_bufmgr_destroy(intel->bufmgr);
return True;
}
--
2.14.1
12:20 a.m.
New subject: [RFC 2/9] Mark the context as concurrent
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
If we mark our context as concurrent we will allow i915 to balance
our submission per batch buffer instead of statically per context.
This is safe to do since it only does it when we use I915_EXEC_BSD,
and not when we explicitly target a specific VCS instance.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_driver.c | 8 ++++++--
src/intel_memman.c | 11 +++++++++--
src/intel_memman.h | 2 +-
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 21b8da684380..d9e8b1a5d8bc 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -96,8 +96,9 @@ intel_driver_init(VADriverContextP ctx)
struct intel_driver_data *intel = intel_driver_data(ctx);
struct drm_state * const drm_state = (struct drm_state *)ctx->drm_state;
int has_exec2 = 0, has_bsd = 0, has_blt = 0, has_vebox = 0;
- char *env_str = NULL;
+ Bool concurrent = 1;
int ret_value = 0;
+ char *env_str;
g_intel_debug_option_flags = 0;
if ((env_str = getenv("VA_INTEL_DEBUG")))
@@ -106,6 +107,9 @@ intel_driver_init(VADriverContextP ctx)
if (g_intel_debug_option_flags)
fprintf(stderr, "g_intel_debug_option_flags:%x\n",
g_intel_debug_option_flags);
+ if ((env_str = getenv("VA_INTEL_CONCURRENT")))
+ concurrent = atoi(env_str);
+
ASSERT_RET(drm_state, false);
ASSERT_RET((VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI1) ||
VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2) ||
@@ -123,7 +127,7 @@ intel_driver_init(VADriverContextP ctx)
intel->locked = 0;
pthread_mutex_init(&intel->ctxmutex, NULL);
- intel_memman_init(intel);
+ intel_memman_init(intel, concurrent);
intel->device_id = drm_intel_bufmgr_gem_get_devid(intel->bufmgr);
intel->device_info = i965_get_device_info(intel->device_id);
diff --git a/src/intel_memman.c b/src/intel_memman.c
index 8ff195e50b0f..04f57be7a402 100644
--- a/src/intel_memman.c
+++ b/src/intel_memman.c
@@ -32,13 +32,20 @@
#include "intel_driver.h"
Bool
-intel_memman_init(struct intel_driver_data *intel)
+intel_memman_init(struct intel_driver_data *intel, Bool concurrent)
{
intel->bufmgr = intel_bufmgr_gem_init(intel->fd, BATCH_SIZE);
assert(intel->bufmgr);
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
- intel->ctx = drm_intel_gem_context_create(intel->bufmgr);
+ if (concurrent) {
+ intel->ctx = drm_intel_gem_context_create(intel->bufmgr);
+ if (intel->ctx) {
+ int ret = drm_intel_gem_context_set_concurrent(intel->ctx);
+
+ assert(ret == 0);
+ }
+ }
if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_DUMP_AUB) {
drm_intel_bufmgr_gem_set_aub_filename(intel->bufmgr,
diff --git a/src/intel_memman.h b/src/intel_memman.h
index 4e516e5156af..a10577d411f3 100644
--- a/src/intel_memman.h
+++ b/src/intel_memman.h
@@ -1,7 +1,7 @@
#ifndef _INTEL_MEMMAN_H_
#define _INTEL_MEMMAN_H_
-Bool intel_memman_init(struct intel_driver_data *intel);
+Bool intel_memman_init(struct intel_driver_data *intel, Bool concurrent);
Bool intel_memman_terminate(struct intel_driver_data *intel);
#endif /* _INTEL_MEMMAN_H_ */
--
2.14.1
12:20 a.m.
New subject: [RFC 3/9] Use engine class when allocating batch buffers
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Instead of passing in the target engine, pass in the target engine class.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/gen6_mfc.c | 6 ++++--
src/gen6_mfd.c | 3 ++-
src/gen75_mfc.c | 6 ++++--
src/gen75_mfd.c | 3 ++-
src/gen75_vpp_gpe.c | 3 ++-
src/gen75_vpp_vebox.c | 3 ++-
src/gen7_mfd.c | 3 ++-
src/gen8_mfc.c | 10 ++++++++--
src/gen8_mfd.c | 5 ++++-
src/gen9_hevc_encoder.c | 2 +-
src/gen9_mfc_hevc.c | 5 ++++-
src/gen9_mfd.c | 3 ++-
src/i965_avc_encoder.c | 2 +-
src/i965_drv_video.c | 8 ++++++--
src/i965_encoder.c | 3 ++-
src/i965_media.c | 3 ++-
src/i965_post_processing.c | 3 ++-
src/intel_batchbuffer.c | 26 ++++++++++++++++++--------
src/intel_batchbuffer.h | 5 ++++-
19 files changed, 72 insertions(+), 30 deletions(-)
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
index c79053d17868..2ed6b4d3ab89 100644
--- a/src/gen6_mfc.c
+++ b/src/gen6_mfc.c
@@ -620,8 +620,10 @@ gen6_mfc_init(VADriverContextP ctx,
if (mfc_context->aux_batchbuffer)
intel_batchbuffer_free(mfc_context->aux_batchbuffer);
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel,
I915_EXEC_BSD,
- slice_batchbuffer_size);
+ mfc_context->aux_batchbuffer =
+ intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_VIDEO,
+ slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo =
mfc_context->aux_batchbuffer->buffer;
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.pitch = 16;
diff --git a/src/gen6_mfd.c b/src/gen6_mfd.c
index bcc455be1935..69f9a1f98acf 100644
--- a/src/gen6_mfd.c
+++ b/src/gen6_mfd.c
@@ -1896,7 +1896,8 @@ gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
gen6_mfd_context->base.run = gen6_mfd_decode_picture;
- gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ gen6_mfd_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
index aa291d540683..faa638bd1f41 100644
--- a/src/gen75_mfc.c
+++ b/src/gen75_mfc.c
@@ -512,8 +512,10 @@ static void gen75_mfc_init(VADriverContextP ctx,
if (mfc_context->aux_batchbuffer)
intel_batchbuffer_free(mfc_context->aux_batchbuffer);
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel,
I915_EXEC_BSD,
- slice_batchbuffer_size);
+ mfc_context->aux_batchbuffer =
+ intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_VIDEO,
+ slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo =
mfc_context->aux_batchbuffer->buffer;
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.pitch = 16;
diff --git a/src/gen75_mfd.c b/src/gen75_mfd.c
index 08855a0b8da5..71943632565b 100644
--- a/src/gen75_mfd.c
+++ b/src/gen75_mfd.c
@@ -3276,7 +3276,8 @@ gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config
assert(gen7_mfd_context);
gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
gen7_mfd_context->base.run = gen75_mfd_decode_picture;
- gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ gen7_mfd_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
diff --git a/src/gen75_vpp_gpe.c b/src/gen75_vpp_gpe.c
index ad893e83fb6c..c57a1741238a 100644
--- a/src/gen75_vpp_gpe.c
+++ b/src/gen75_vpp_gpe.c
@@ -858,7 +858,8 @@ vpp_gpe_context_init(VADriverContextP ctx)
vpp_gpe_ctx->surface_tmp = VA_INVALID_ID;
vpp_gpe_ctx->surface_tmp_object = NULL;
- vpp_gpe_ctx->batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER,
0);
+ vpp_gpe_ctx->batch =
+ intel_batchbuffer_new(&i965->intel, I915_ENGINE_CLASS_RENDER, 0);
vpp_gpe_ctx->is_first_frame = 1;
gpe_ctx->vfe_state.max_num_threads = 60 - 1;
diff --git a/src/gen75_vpp_vebox.c b/src/gen75_vpp_vebox.c
index 9b33e36b8c4c..4f3e3cf40d28 100644
--- a/src/gen75_vpp_vebox.c
+++ b/src/gen75_vpp_vebox.c
@@ -1832,7 +1832,8 @@ struct intel_vebox_context *
gen75_vebox_context_init(VADriverContextP ctx)
int i;
assert(proc_context);
- proc_context->batch = intel_batchbuffer_new(intel, I915_EXEC_VEBOX, 0);
+ proc_context->batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
for (i = 0; i < ARRAY_ELEMS(proc_context->frame_store); i++)
proc_context->frame_store[i].surface_id = VA_INVALID_ID;
diff --git a/src/gen7_mfd.c b/src/gen7_mfd.c
index 1e6911e2ab0f..5ed9029f0ae1 100644
--- a/src/gen7_mfd.c
+++ b/src/gen7_mfd.c
@@ -2756,7 +2756,8 @@ gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
assert(gen7_mfd_context);
gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
gen7_mfd_context->base.run = gen7_mfd_decode_picture;
- gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ gen7_mfd_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c
index b62e71f618ed..6d4926ac2096 100644
--- a/src/gen8_mfc.c
+++ b/src/gen8_mfc.c
@@ -625,7 +625,10 @@ static void gen8_mfc_init(VADriverContextP ctx,
if (mfc_context->aux_batchbuffer)
intel_batchbuffer_free(mfc_context->aux_batchbuffer);
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel,
I915_EXEC_BSD, slice_batchbuffer_size);
+ mfc_context->aux_batchbuffer =
+ intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_VIDEO,
+ slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo =
mfc_context->aux_batchbuffer->buffer;
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.pitch = 16;
@@ -3707,7 +3710,10 @@ static void gen8_mfc_vp8_init(VADriverContextP ctx,
mfc_context->aux_batchbuffer = NULL;
}
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel,
I915_EXEC_BSD, slice_batchbuffer_size);
+ mfc_context->aux_batchbuffer =
+ intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_VIDEO,
+ slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo =
mfc_context->aux_batchbuffer->buffer;
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.pitch = 16;
diff --git a/src/gen8_mfd.c b/src/gen8_mfd.c
index 78719b2f5967..c693b9ad3c68 100644
--- a/src/gen8_mfd.c
+++ b/src/gen8_mfd.c
@@ -3217,7 +3217,10 @@ gen8_dec_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
gen7_mfd_context->base.destroy = gen8_mfd_context_destroy;
gen7_mfd_context->base.run = gen8_mfd_decode_picture;
- gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ gen7_mfd_context->base.batch =
+ intel_batchbuffer_new(intel,
+ I915_ENGINE_CLASS_RENDER,
+ 0);
for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
diff --git a/src/gen9_hevc_encoder.c b/src/gen9_hevc_encoder.c
index 80d9d9c1aee9..9a72722c1b9f 100644
--- a/src/gen9_hevc_encoder.c
+++ b/src/gen9_hevc_encoder.c
@@ -7062,7 +7062,7 @@ gen9_hevc_pak_pipeline_prepare(VADriverContextP ctx,
intel_batchbuffer_free(priv_ctx->res_pak_slice_batch_buffer);
priv_ctx->res_pak_slice_batch_buffer =
- intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
+ intel_batchbuffer_new(&i965->intel, I915_ENGINE_CLASS_VIDEO,
GEN9_HEVC_ENC_PAK_SLICE_STATE_SIZE *
encode_state->num_slice_params_ext);
if (!priv_ctx->res_pak_slice_batch_buffer)
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
index 53556442e00f..6d64f5293e3c 100644
--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -1064,7 +1064,10 @@ static void gen9_hcpe_init(VADriverContextP ctx,
if (mfc_context->aux_batchbuffer)
intel_batchbuffer_free(mfc_context->aux_batchbuffer);
- mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel,
I915_EXEC_BSD, slice_batchbuffer_size);
+ mfc_context->aux_batchbuffer =
+ intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_VIDEO,
+ slice_batchbuffer_size);
mfc_context->aux_batchbuffer_surface.bo =
mfc_context->aux_batchbuffer->buffer;
dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
mfc_context->aux_batchbuffer_surface.pitch = 16;
diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index 2490b217a3c7..3a79e0c90272 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -1905,7 +1905,8 @@ gen9_hcpd_context_init(VADriverContextP ctx, struct object_config
*object_config
gen9_hcpd_context->base.destroy = gen9_hcpd_context_destroy;
gen9_hcpd_context->base.run = gen9_hcpd_decode_picture;
- gen9_hcpd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_VEBOX, 0);
+ gen9_hcpd_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
for (i = 0; i < ARRAY_ELEMS(gen9_hcpd_context->reference_surfaces); i++) {
gen9_hcpd_context->reference_surfaces[i].surface_id = VA_INVALID_ID;
diff --git a/src/i965_avc_encoder.c b/src/i965_avc_encoder.c
index 692f3c162706..21fedb845682 100644
--- a/src/i965_avc_encoder.c
+++ b/src/i965_avc_encoder.c
@@ -9472,7 +9472,7 @@ gen9_avc_pak_pipeline_prepare(VADriverContextP ctx,
}
avc_ctx->pres_slice_batch_buffer_2nd_level =
- intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
+ intel_batchbuffer_new(&i965->intel, I915_ENGINE_CLASS_VIDEO,
4096 *
encode_state->num_slice_params_ext);
if (!avc_ctx->pres_slice_batch_buffer_2nd_level)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 02f489571fba..cfa066349255 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -6721,8 +6721,12 @@ i965_driver_data_init(VADriverContextP ctx)
SUBPIC_ID_OFFSET))
goto err_subpic_heap;
- i965->batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER, 0);
- i965->pp_batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER, 0);
+ i965->batch = intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_RENDER,
+ 0);
+ i965->pp_batch = intel_batchbuffer_new(&i965->intel,
+ I915_ENGINE_CLASS_RENDER,
+ 0);
_i965InitMutex(&i965->render_mutex);
_i965InitMutex(&i965->pp_mutex);
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index 4c2fc037fcb1..4d6da8a93956 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -1448,7 +1448,8 @@ intel_enc_hw_context_init(VADriverContextP ctx,
encoder_context->base.destroy = intel_encoder_context_destroy;
encoder_context->base.run = intel_encoder_end_picture;
encoder_context->base.get_status = intel_encoder_get_status;
- encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ encoder_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
encoder_context->input_yuv_surface = VA_INVALID_SURFACE;
encoder_context->is_tmp_id = 0;
encoder_context->low_power_mode = 0;
diff --git a/src/i965_media.c b/src/i965_media.c
index 8f2875617e11..e103de15f35a 100644
--- a/src/i965_media.c
+++ b/src/i965_media.c
@@ -341,7 +341,8 @@ g4x_dec_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
assert(media_context);
media_context->base.destroy = i965_media_context_destroy;
media_context->base.run = i965_media_decode_picture;
- media_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ media_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
switch (obj_config->profile) {
case VAProfileMPEG2Simple:
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index 9d902fb036cf..64eec9aae1fa 100644
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -6336,7 +6336,8 @@ i965_proc_context_init(VADriverContextP ctx, struct object_config
*obj_config)
proc_context->base.destroy = i965_proc_context_destroy;
proc_context->base.run = i965_proc_picture;
- proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
+ proc_context->base.batch =
+ intel_batchbuffer_new(intel, I915_ENGINE_CLASS_RENDER, 0);
proc_context->driver_context = ctx;
i965->codec_info->post_processing_context_init(ctx,
&proc_context->pp_context, proc_context->base.batch);
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index e7d038079e5f..1815632325a8 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -75,16 +75,26 @@ intel_batchbuffer_space(struct intel_batchbuffer *batch)
struct intel_batchbuffer *
-intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int buffer_size)
+intel_batchbuffer_new(struct intel_driver_data *intel,
+ enum drm_i915_gem_engine_class class,
+ int buffer_size)
{
struct intel_batchbuffer *batch = calloc(1, sizeof(*batch));
int ring_flag;
- ring_flag = flag & I915_EXEC_RING_MASK;
- assert(ring_flag == I915_EXEC_RENDER ||
- ring_flag == I915_EXEC_BSD ||
- ring_flag == I915_EXEC_BLT ||
- ring_flag == I915_EXEC_VEBOX);
+ switch (class) {
+ case I915_ENGINE_CLASS_RENDER:
+ ring_flag = I915_EXEC_RENDER;
+ break;
+ case I915_ENGINE_CLASS_VIDEO:
+ ring_flag = I915_EXEC_BSD;
+ break;
+ case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ ring_flag = I915_EXEC_VEBOX;
+ break;
+ default:
+ assert(0);
+ }
if (!buffer_size || buffer_size < BATCH_SIZE) {
buffer_size = BATCH_SIZE;
@@ -97,13 +107,13 @@ intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int
buffer_size
assert(batch);
batch->intel = intel;
- batch->flag = flag;
+ batch->flag = ring_flag;
batch->run = drm_intel_bo_mrb_exec;
if (intel->ctx)
batch->run_ctx = drm_intel_gem_bo_context_exec;
if (IS_GEN6(intel->device_info) &&
- flag == I915_EXEC_RENDER)
+ class == I915_ENGINE_CLASS_RENDER)
batch->wa_render_bo = dri_bo_alloc(intel->bufmgr,
"wa scratch",
4096,
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index a4a3ed27fd45..51664006537a 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -30,7 +30,10 @@ struct intel_batchbuffer {
dri_bo *wa_render_bo;
};
-struct intel_batchbuffer *intel_batchbuffer_new(struct intel_driver_data *intel, int
flag, int buffer_size);
+struct intel_batchbuffer *
+intel_batchbuffer_new(struct intel_driver_data *intel,
+ enum drm_i915_gem_engine_class class,
+ int buffer_size);
void intel_batchbuffer_free(struct intel_batchbuffer *batch);
void intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size);
void intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int
size);
--
2.14.1
12:20 a.m.
New subject: [RFC 4/9] Use class and instance in batch override
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Same as when allocating batches, use the class and instance concept
when overriding the target engine.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/gen9_hevc_encoder.c | 2 +-
src/gen9_mfc_hevc.c | 2 +-
src/gen9_mfd.c | 4 +--
src/gen9_vdenc.c | 2 +-
src/gen9_vp9_encoder.c | 2 +-
src/i965_avc_encoder.c | 2 +-
src/i965_encoder_vp8.c | 6 ++--
src/intel_batchbuffer.c | 89 +++++++++++++++++++++++--------------------------
src/intel_batchbuffer.h | 69 ++++++++++++++++++++++++++++++--------
9 files changed, 108 insertions(+), 70 deletions(-)
diff --git a/src/gen9_hevc_encoder.c b/src/gen9_hevc_encoder.c
index 9a72722c1b9f..38016d313edc 100644
--- a/src/gen9_hevc_encoder.c
+++ b/src/gen9_hevc_encoder.c
@@ -7223,7 +7223,7 @@ gen9_hevc_pak_pipeline(VADriverContextP ctx,
goto EXIT;
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
index 6d64f5293e3c..48b379c37c9f 100644
--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -1939,7 +1939,7 @@ gen9_hcpe_hevc_pipeline_programing(VADriverContextP ctx,
// begin programing
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x4000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x4000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
intel_batchbuffer_emit_mi_flush(batch);
diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index 3a79e0c90272..530870152395 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -923,7 +923,7 @@ gen9_hcpd_hevc_decode_picture(VADriverContextP ctx,
pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
intel_batchbuffer_emit_mi_flush(batch);
@@ -1722,7 +1722,7 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
vp9_update_probabilities(ctx, decode_state, gen9_hcpd_context);
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
intel_batchbuffer_emit_mi_flush(batch);
diff --git a/src/gen9_vdenc.c b/src/gen9_vdenc.c
index a1f2f72adf2a..4373b25daf23 100644
--- a/src/gen9_vdenc.c
+++ b/src/gen9_vdenc.c
@@ -3672,7 +3672,7 @@ gen9_vdenc_avc_encode_picture(VADriverContextP ctx,
vdenc_context->is_first_pass = (vdenc_context->current_pass == 0);
vdenc_context->is_last_pass = (vdenc_context->current_pass ==
(vdenc_context->num_passes - 1));
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
intel_batchbuffer_emit_mi_flush(batch);
diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c
index 8389dde31118..8de3a42e60e7 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -5510,7 +5510,7 @@ gen9_vp9_pak_pipeline(VADriverContextP ctx,
return va_status;
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
diff --git a/src/i965_avc_encoder.c b/src/i965_avc_encoder.c
index 21fedb845682..73803995ae33 100644
--- a/src/i965_avc_encoder.c
+++ b/src/i965_avc_encoder.c
@@ -9545,7 +9545,7 @@ gen9_avc_encode_picture(VADriverContextP ctx,
return va_status;
if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
else
intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
intel_batchbuffer_emit_mi_flush(batch);
diff --git a/src/i965_encoder_vp8.c b/src/i965_encoder_vp8.c
index b5eb5ef03a63..aa6fe834b6dd 100644
--- a/src/i965_encoder_vp8.c
+++ b/src/i965_encoder_vp8.c
@@ -5099,16 +5099,16 @@ i965_encoder_vp8_vme_var_init(VADriverContextP ctx,
vp8_context->min_scaled_dimension = 48;
vp8_context->min_scaled_dimension_in_mbs =
WIDTH_IN_MACROBLOCKS(vp8_context->min_scaled_dimension);
- vp8_context->vdbox_idc = BSD_RING0;
+ vp8_context->vdbox_idc = 0;
vp8_context->vdbox_mmio_base = VDBOX0_MMIO_BASE;
/* TODO: This is a WA for VDBOX loading balance only, */
if (i965->intel.has_bsd2) {
srandom(time(NULL));
- vp8_context->vdbox_idc = (random() % 2 ? BSD_RING1 : BSD_RING0);
+ vp8_context->vdbox_idc = random() % 2;
}
- if (vp8_context->vdbox_idc == BSD_RING1)
+ if (vp8_context->vdbox_idc == 1)
vp8_context->vdbox_mmio_base = VDBOX1_MMIO_BASE;
vp8_context->frame_type = MPEG_I_PICTURE;
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 1815632325a8..2c9400b3d2c6 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -73,29 +73,56 @@ intel_batchbuffer_space(struct intel_batchbuffer *batch)
return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map);
}
-
-struct intel_batchbuffer *
-intel_batchbuffer_new(struct intel_driver_data *intel,
- enum drm_i915_gem_engine_class class,
- int buffer_size)
+static unsigned int
+class_instance_to_ring_flag(enum drm_i915_gem_engine_class class,
+ unsigned int instance)
{
- struct intel_batchbuffer *batch = calloc(1, sizeof(*batch));
- int ring_flag;
+ unsigned ring_flag;
switch (class) {
case I915_ENGINE_CLASS_RENDER:
+ assert(instance == 0 || instance == I915_EXEC_INSTANCE_ANY);
ring_flag = I915_EXEC_RENDER;
break;
+ case I915_ENGINE_CLASS_COPY:
+ assert(instance == 0 || instance == I915_EXEC_INSTANCE_ANY);
+ ring_flag = I915_EXEC_BLT;
+ break;
case I915_ENGINE_CLASS_VIDEO:
ring_flag = I915_EXEC_BSD;
+ switch (instance) {
+ case I915_EXEC_INSTANCE_ANY:
+ break;
+ case 0:
+ ring_flag |= I915_EXEC_BSD_RING1;
+ break;
+ case 1:
+ ring_flag |= I915_EXEC_BSD_RING2;
+ break;
+ default:
+ assert(0);
+ }
break;
case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ assert(instance == 0 || instance == I915_EXEC_INSTANCE_ANY);
ring_flag = I915_EXEC_VEBOX;
break;
default:
assert(0);
}
+ return ring_flag;
+}
+
+struct intel_batchbuffer *
+intel_batchbuffer_new(struct intel_driver_data *intel,
+ enum drm_i915_gem_engine_class class,
+ int buffer_size)
+{
+ struct intel_batchbuffer *batch = calloc(1, sizeof(*batch));
+ unsigned int ring_flag =
+ class_instance_to_ring_flag(class, I915_EXEC_INSTANCE_ANY);
+
if (!buffer_size || buffer_size < BATCH_SIZE) {
buffer_size = BATCH_SIZE;
}
@@ -386,49 +413,17 @@ intel_batchbuffer_start_atomic_helper(struct intel_batchbuffer
*batch,
}
void
-intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size)
+intel_batchbuffer_start_atomic_override(struct intel_batchbuffer *batch,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance,
+ unsigned int size)
{
- intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_RENDER, size);
+ intel_batchbuffer_start_atomic_helper(batch,
+ class_instance_to_ring_flag(class,
+ instance),
+ size);
}
-void
-intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int size)
-{
- intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BLT, size);
-}
-
-void
-intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int size)
-{
- intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BSD, size);
-}
-
-void
-intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int size)
-{
- intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_VEBOX, size);
-}
-
-void intel_batchbuffer_start_atomic_bcs_override(struct intel_batchbuffer *batch,
unsigned int size,
- bsd_ring_flag override_flag)
-{
- uint32_t ring_flag;
-
- switch (override_flag) {
- case BSD_RING0:
- ring_flag = I915_EXEC_BSD + LOCAL_I915_EXEC_BSD_RING0;
- break;
- case BSD_RING1:
- ring_flag = I915_EXEC_BSD + LOCAL_I915_EXEC_BSD_RING1;
- break;
- default:
- ring_flag = I915_EXEC_BSD + LOCAL_I915_EXEC_BSD_DEFAULT;
- break;
- }
- intel_batchbuffer_start_atomic_helper(batch, ring_flag, size);
-}
-
-
void
intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch)
{
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index 51664006537a..12220cf7ceb9 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -35,11 +35,63 @@ intel_batchbuffer_new(struct intel_driver_data *intel,
enum drm_i915_gem_engine_class class,
int buffer_size);
void intel_batchbuffer_free(struct intel_batchbuffer *batch);
-void intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size);
-void intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int
size);
-void intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int
size);
-void intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int
size);
+void intel_batchbuffer_start_atomic_override(struct intel_batchbuffer *batch,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance,
+ unsigned int size);
void intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch);
+
+static inline void
+intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch,
+ unsigned int size)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_RENDER,
+ 0,
+ size);
+}
+
+static inline void
+intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch,
+ unsigned int size)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_VIDEO,
+ I915_EXEC_INSTANCE_ANY,
+ size);
+}
+
+static inline void
+intel_batchbuffer_start_atomic_bcs_override(struct intel_batchbuffer *batch,
+ unsigned int size,
+ unsigned int instance)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_VIDEO,
+ instance,
+ size);
+}
+
+static inline void
+intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch,
+ unsigned int size)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_COPY,
+ 0,
+ size);
+}
+
+static inline void
+intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch,
+ unsigned int size)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE,
+ 0,
+ size);
+}
+
void intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, unsigned int x);
void intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, dri_bo *bo,
uint32_t read_domains, uint32_t write_domains,
@@ -58,15 +110,6 @@ int intel_batchbuffer_check_free_space(struct intel_batchbuffer
*batch, int size
int intel_batchbuffer_used_size(struct intel_batchbuffer *batch);
void intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment);
-typedef enum {
- BSD_DEFAULT,
- BSD_RING0,
- BSD_RING1,
-} bsd_ring_flag;
-
-void intel_batchbuffer_start_atomic_bcs_override(struct intel_batchbuffer *batch,
unsigned int size,
- bsd_ring_flag override_flag);
-
#define __BEGIN_BATCH(batch, n, f) do { \
assert(f == (batch->flag & I915_EXEC_RING_MASK));
\
intel_batchbuffer_check_batchbuffer_flag(batch, batch->flag); \
--
2.14.1
12:20 a.m.
New subject: [RFC 5/9] Store class/instance in batch and use for flushing
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Use the class and instance instead of flags for deciding when to flush.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_batchbuffer.c | 48 +++++++++++++-----------------------------------
src/intel_batchbuffer.h | 4 ++--
2 files changed, 15 insertions(+), 37 deletions(-)
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 2c9400b3d2c6..caef0aaa34f9 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -134,6 +134,8 @@ intel_batchbuffer_new(struct intel_driver_data *intel,
assert(batch);
batch->intel = intel;
+ batch->class = class;
+ batch->instance = I915_EXEC_INSTANCE_ANY;
batch->flag = ring_flag;
batch->run = drm_intel_bo_mrb_exec;
if (intel->ctx)
@@ -375,53 +377,29 @@ intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch)
assert(batch->emit_total == (batch->ptr - batch->emit_start));
}
-void
-intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int flag)
-{
- int ring_flag;
-
- ring_flag = flag & I915_EXEC_RING_MASK;
-
- if (ring_flag != I915_EXEC_RENDER &&
- ring_flag != I915_EXEC_BLT &&
- ring_flag != I915_EXEC_BSD &&
- ring_flag != I915_EXEC_VEBOX)
- return;
-
- if (batch->flag == flag)
- return;
-
- intel_batchbuffer_flush(batch);
- batch->flag = flag;
-}
-
int
intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size)
{
return intel_batchbuffer_space(batch) >= size;
}
-static void
-intel_batchbuffer_start_atomic_helper(struct intel_batchbuffer *batch,
- int flag,
- unsigned int size)
-{
- assert(!batch->atomic);
- intel_batchbuffer_check_batchbuffer_flag(batch, flag);
- intel_batchbuffer_require_space(batch, size);
- batch->atomic = 1;
-}
-
void
intel_batchbuffer_start_atomic_override(struct intel_batchbuffer *batch,
enum drm_i915_gem_engine_class class,
unsigned int instance,
unsigned int size)
{
- intel_batchbuffer_start_atomic_helper(batch,
- class_instance_to_ring_flag(class,
- instance),
- size);
+ assert(!batch->atomic);
+
+ if (batch->class != class || batch->instance != instance)
+ intel_batchbuffer_flush(batch);
+
+ intel_batchbuffer_require_space(batch, size);
+
+ batch->class = class;
+ batch->instance = instance;
+ batch->flag = class_instance_to_ring_flag(class, instance);
+ batch->atomic = 1;
}
void
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index 12220cf7ceb9..dc28ea581471 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -15,6 +15,8 @@ struct intel_batchbuffer {
unsigned char *map;
unsigned char *ptr;
int atomic;
+ enum drm_i915_gem_engine_class class;
+ unsigned int instance;
int flag;
int emit_total;
@@ -105,14 +107,12 @@ void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer
*batch);
void intel_batchbuffer_flush(struct intel_batchbuffer *batch);
void intel_batchbuffer_begin_batch(struct intel_batchbuffer *batch, int total);
void intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch);
-void intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int
flag);
int intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size);
int intel_batchbuffer_used_size(struct intel_batchbuffer *batch);
void intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment);
#define __BEGIN_BATCH(batch, n, f) do { \
assert(f == (batch->flag & I915_EXEC_RING_MASK));
\
- intel_batchbuffer_check_batchbuffer_flag(batch, batch->flag); \
intel_batchbuffer_require_space(batch, (n) * 4); \
intel_batchbuffer_begin_batch(batch, (n)); \
} while (0)
--
2.14.1
12:20 a.m.
New subject: [RFC 6/9] Use class/instance based execbuf
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
If the kernel supports the class/instance execbuf2, use it.
Auto-detection is done on the first batch with a fall-back to
legacy engine selection.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_batchbuffer.c | 24 +++++++++++++++++++++---
src/intel_driver.c | 2 ++
src/intel_driver.h | 2 ++
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index caef0aaa34f9..8937ab30528e 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -185,10 +185,28 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch)
batch->ptr += 4;
dri_bo_unmap(batch->buffer);
used = batch->ptr - batch->map;
- if (batch->run_ctx)
- batch->run_ctx(batch->buffer, batch->intel->ctx, used,
batch->flag);
- else
+ if (batch->run_ctx) {
+ unsigned int flags;
+ int ret;
+
+retry:
+ if (batch->intel->has_class_instance) {
+ flags = i915_execbuffer2_engine(batch->class, batch->instance);
+
+ ret = batch->run_ctx(batch->buffer, batch->intel->ctx, used,
flags);
+ if (ret < 0) {
+ fprintf(stderr, "Falling back to eb2!\n");
+ batch->intel->has_class_instance = 0;
+ goto retry;
+ }
+ } else {
+ ret = batch->run_ctx(batch->buffer, batch->intel->ctx, used,
+ batch->flag);
+ assert(ret == 0);
+ }
+ } else {
batch->run(batch->buffer, used, 0, 0, 0, batch->flag);
+ }
intel_batchbuffer_reset(batch, batch->size);
}
diff --git a/src/intel_driver.c b/src/intel_driver.c
index d9e8b1a5d8bc..e3cbd31667ba 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -153,6 +153,8 @@ intel_driver_init(VADriverContextP ctx)
if (intel_driver_get_param(intel, LOCAL_I915_PARAM_HAS_HUC, &ret_value))
intel->has_huc = !!ret_value;
+ intel->has_class_instance = 1;
+
intel->eu_total = 0;
if (intel_driver_get_param(intel, LOCAL_I915_PARAM_EU_TOTAL, &ret_value)) {
intel->eu_total = ret_value;
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 2999d8ebcfa2..cf617cb118de 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -190,6 +190,8 @@ struct intel_driver_data {
unsigned int has_bsd2 : 1; /* Flag: has the second BSD video ring unit */
unsigned int has_huc : 1; /* Flag: has a fully loaded HuC firmware? */
+ unsigned int has_class_instance;
+
int eu_total;
const struct intel_device_info *device_info;
--
2.14.1
12:20 a.m.
New subject: [RFC 7/9] Store engine features in batch
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Ground work for following patches.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_batchbuffer.c | 7 +++++--
src/intel_batchbuffer.h | 7 +++++++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 8937ab30528e..d9deeb5b4eb5 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -405,17 +405,20 @@ void
intel_batchbuffer_start_atomic_override(struct intel_batchbuffer *batch,
enum drm_i915_gem_engine_class class,
unsigned int instance,
+ unsigned int features,
unsigned int size)
{
assert(!batch->atomic);
- if (batch->class != class || batch->instance != instance)
- intel_batchbuffer_flush(batch);
+ if (batch->class != class || batch->instance != instance ||
+ batch->features != features)
+ intel_batchbuffer_flush(batch);
intel_batchbuffer_require_space(batch, size);
batch->class = class;
batch->instance = instance;
+ batch->features = features;
batch->flag = class_instance_to_ring_flag(class, instance);
batch->atomic = 1;
}
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index dc28ea581471..35d3c2c98ec2 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -17,6 +17,7 @@ struct intel_batchbuffer {
int atomic;
enum drm_i915_gem_engine_class class;
unsigned int instance;
+ unsigned int features;
int flag;
int emit_total;
@@ -40,6 +41,7 @@ void intel_batchbuffer_free(struct intel_batchbuffer *batch);
void intel_batchbuffer_start_atomic_override(struct intel_batchbuffer *batch,
enum drm_i915_gem_engine_class class,
unsigned int instance,
+ unsigned int features,
unsigned int size);
void intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch);
@@ -50,6 +52,7 @@ intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch,
intel_batchbuffer_start_atomic_override(batch,
I915_ENGINE_CLASS_RENDER,
0,
+ 0,
size);
}
@@ -60,6 +63,7 @@ intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch,
intel_batchbuffer_start_atomic_override(batch,
I915_ENGINE_CLASS_VIDEO,
I915_EXEC_INSTANCE_ANY,
+ 0,
size);
}
@@ -71,6 +75,7 @@ intel_batchbuffer_start_atomic_bcs_override(struct intel_batchbuffer
*batch,
intel_batchbuffer_start_atomic_override(batch,
I915_ENGINE_CLASS_VIDEO,
instance,
+ 0,
size);
}
@@ -81,6 +86,7 @@ intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch,
intel_batchbuffer_start_atomic_override(batch,
I915_ENGINE_CLASS_COPY,
0,
+ 0,
size);
}
@@ -91,6 +97,7 @@ intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch,
intel_batchbuffer_start_atomic_override(batch,
I915_ENGINE_CLASS_VIDEO_ENHANCE,
0,
+ 0,
size);
}
--
2.14.1
12:20 a.m.
New subject: [RFC 8/9] Feature based VCS override
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Add intel_batchbuffer_start_atomic_bcs_features API to choose the
correct engine instance based on required features.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/intel_batchbuffer.c | 13 +++++++++++--
src/intel_batchbuffer.h | 12 ++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index d9deeb5b4eb5..2b61694d97b1 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -193,6 +193,9 @@ retry:
if (batch->intel->has_class_instance) {
flags = i915_execbuffer2_engine(batch->class, batch->instance);
+ if (batch->features)
+ flags |= I915_ENGINE_CAP_FLAG(batch->features);
+
ret = batch->run_ctx(batch->buffer, batch->intel->ctx, used,
flags);
if (ret < 0) {
fprintf(stderr, "Falling back to eb2!\n");
@@ -200,8 +203,14 @@ retry:
goto retry;
}
} else {
- ret = batch->run_ctx(batch->buffer, batch->intel->ctx, used,
- batch->flag);
+ assert(batch->features == 0 ||
+ batch->features == I915_BSD_CAP_HEVC);
+ if (batch->features & I915_BSD_CAP_HEVC)
+ flags = i915_execbuffer2_engine(batch->class, 0);
+ else
+ flags = batch->flag;
+
+ ret = batch->run_ctx(batch->buffer, batch->intel->ctx, used,
flags);
assert(ret == 0);
}
} else {
diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index 35d3c2c98ec2..ce078eed842d 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -79,6 +79,18 @@ intel_batchbuffer_start_atomic_bcs_override(struct intel_batchbuffer
*batch,
size);
}
+static inline void
+intel_batchbuffer_start_atomic_bcs_features(struct intel_batchbuffer *batch,
+ unsigned int size,
+ unsigned int features)
+{
+ intel_batchbuffer_start_atomic_override(batch,
+ I915_ENGINE_CLASS_VIDEO,
+ I915_EXEC_INSTANCE_ANY,
+ features,
+ size);
+}
+
static inline void
intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch,
unsigned int size)
--
2.14.1
12:20 a.m.
New subject: [RFC 9/9] Use engine features for HEVC decode
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Mark HEVC decode as needing the HEVC engine capability instead
of explicitly sending that work to vcs0.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
---
src/gen9_mfd.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index 530870152395..4b5c6e12f3a9 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -907,7 +907,6 @@ gen9_hcpd_hevc_decode_picture(VADriverContextP ctx,
struct gen9_hcpd_context *gen9_hcpd_context)
{
VAStatus vaStatus;
- struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
VAPictureParameterBufferHEVC *pic_param;
VASliceParameterBufferHEVC *slice_param, *next_slice_param, *next_slice_group_param;
@@ -922,10 +921,7 @@ gen9_hcpd_hevc_decode_picture(VADriverContextP ctx,
assert(decode_state->pic_param && decode_state->pic_param->buffer);
pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
- if (i965->intel.has_bsd2)
- intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, 0);
- else
- intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+ intel_batchbuffer_start_atomic_bcs_features(batch, 0x1000, I915_BSD_CAP_HEVC);
intel_batchbuffer_emit_mi_flush(batch);
gen9_hcpd_pipe_mode_select(ctx, decode_state, HCP_CODEC_HEVC, gen9_hcpd_context);
--
2.14.1
4:33 a.m.
Hi Tvrtko,
Could you create a PR on https://github.com/01org/intel-vaapi-driver? We review patches on
github instead of the mailing list, I'm sorry for any inconvenience.
Thanks
Haihao
-----Original Message-----
From: intel-vaapi-media [mailto:intel-vaapi-media-bounces@lists.01.org] On
Behalf Of Tvrtko Ursulin
Sent: Monday, November 13, 2017 5:21 AM
To: intel-vaapi-media(a)lists.01.org
Cc: Ursulin, Tvrtko <tvrtko.ursulin(a)intel.com>
Subject: [intel-vaapi-media] [RFC 0/9] Per batch buffer balancing
From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com>
Hi,
I have been working on some new i915 uAPI proposals which sounds
interesting for the intel-vaapi-driver project.
Primarily this is about changing the way VCS engines are selected at execbuf
time, adding the i915 feature to load-balance those batches, and allowing
userspace to opt-in to such behaviour.
You can find this patches here:
https://patchwork.freedesktop.org/series/33706/
This series contains proof of concept patches against intel-vaapi-driver to
make use of these proposed i915 features.
I am not familiar of the code base so there might be smaller or bigger mistakes
here, please be aware.
But in essence the code seems to pass the test shipped with the project and is
also able to utilize the features as intended when run for instance from
ffmpeg:
root@sc:~/ffmpeg# VA_INTEL_CONCURRENT=0 perf stat -a -e i915/vcs0-
busy/,i915/vcs1-busy/ ffmpeg -loglevel panic -hwaccel vaapi -
hwaccel_output_format vaapi -i ~/bbb_sunflower_1080p_60fps_normal.mp4
-f null -
Performance counter stats for 'system wide':
57,568,097,358 ns i915/vcs0-busy/
0 ns i915/vcs1-busy/
57.585753514 seconds time elapsed
root@sc:~/ffmpeg# VA_INTEL_CONCURRENT=1 perf stat -a -e i915/vcs0-
busy/,i915/vcs1-busy/ ffmpeg -loglevel panic -hwaccel vaapi -
hwaccel_output_format vaapi -i ~/bbb_sunflower_1080p_60fps_normal.mp4
-f null -
Performance counter stats for 'system wide':
29,152,427,164 ns i915/vcs0-busy/
29,115,272,714 ns i915/vcs1-busy/
40.733992298 seconds time elapsed
This shows that decoding a single stream on a SKL GT4 part it is able to utilize
both VCS engines for a nice performance improvement.
It could also have a beneficial effect when multiple parallel streams are
decoded or encoded, but in this case it will depend on the exact streams.
Because the current i915 RFC does a trivial round-robin engine balancing only.
In the future we may decide to take the route of making the i915 scheduler
smarter in this respect.
Main question is whether you guys can see some flaws in this approach, both
design and implementation, and whether you would be interested in having
such extensions in your code base?
Tvrtko Ursulin (9):
Create a dedicated context
Mark the context as concurrent
Use engine class when allocating batch buffers
Use class and instance in batch override
Store class/instance in batch and use for flushing
Use class/instance based execbuf
Store engine features in batch
Feature based VCS override
Use engine features for HEVC decode
src/gen6_mfc.c | 6 +-
src/gen6_mfd.c | 3 +-
src/gen75_mfc.c | 6 +-
src/gen75_mfd.c | 3 +-
src/gen75_vpp_gpe.c | 3 +-
src/gen75_vpp_vebox.c | 3 +-
src/gen7_mfd.c | 3 +-
src/gen8_mfc.c | 10 ++-
src/gen8_mfd.c | 5 +-
src/gen9_hevc_encoder.c | 4 +-
src/gen9_mfc_hevc.c | 7 +-
src/gen9_mfd.c | 11 ++-
src/gen9_vdenc.c | 2 +-
src/gen9_vp9_encoder.c | 2 +-
src/i965_avc_encoder.c | 4 +-
src/i965_drv_video.c | 8 ++-
src/i965_encoder.c | 3 +-
src/i965_encoder_vp8.c | 6 +-
src/i965_media.c | 3 +-
src/i965_post_processing.c | 3 +-
src/intel_batchbuffer.c | 176 +++++++++++++++++++++++++--------------------
src/intel_batchbuffer.h | 99 ++++++++++++++++++++-----
src/intel_driver.c | 10 ++-
src/intel_driver.h | 3 +
src/intel_memman.c | 13 +++-
src/intel_memman.h | 2 +-
26 files changed, 264 insertions(+), 134 deletions(-)
--
2.14.1
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participants (2)
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Tvrtko Ursulin -
Xiang, Haihao