[intel-linux-intel-lts:5.4/yocto 40/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:972 dw_chan_prep_dma_cyclic() error: uninitialized symbol 'mem'.
by Dan Carpenter
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [40/1142] dmaengine: dw-axi-dma: support cyclic mode
config: i386-randconfig-m021-20201209 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com>
New smatch warnings:
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:972 dw_chan_prep_dma_cyclic() error: uninitialized symbol 'mem'.
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:972 dw_chan_prep_dma_cyclic() error: uninitialized symbol 'len'.
Old smatch warnings:
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1050 dw_chan_prep_dma_cyclic() error: uninitialized symbol 'len'.
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1058 dw_chan_prep_dma_cyclic() error: uninitialized symbol 'mem'.
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1139 axi_chan_handle_err() warn: inconsistent returns 'chan->vc.lock'.
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1139 axi_chan_handle_err() warn: inconsistent returns 'flags'.
vim +/mem +972 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
94e13c28801677 Sia Jee Heng 2020-06-26 913 static struct dma_async_tx_descriptor *
94e13c28801677 Sia Jee Heng 2020-06-26 914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
94e13c28801677 Sia Jee Heng 2020-06-26 915 size_t buf_len, size_t period_len,
94e13c28801677 Sia Jee Heng 2020-06-26 916 enum dma_transfer_direction direction,
94e13c28801677 Sia Jee Heng 2020-06-26 917 unsigned long flags)
94e13c28801677 Sia Jee Heng 2020-06-26 918 {
94e13c28801677 Sia Jee Heng 2020-06-26 919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
94e13c28801677 Sia Jee Heng 2020-06-26 920 struct axi_dma_desc *first = NULL, *prev = NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 921 unsigned int reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 922 unsigned int mem_width;
94e13c28801677 Sia Jee Heng 2020-06-26 923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
94e13c28801677 Sia Jee Heng 2020-06-26 924 dma_addr_t reg;
94e13c28801677 Sia Jee Heng 2020-06-26 925 u32 reg_value = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 926 unsigned int i = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 927 u32 ctllo, ctlhi;
94e13c28801677 Sia Jee Heng 2020-06-26 928 size_t total_len = 0;
94e13c28801677 Sia Jee Heng 2020-06-26 929 size_t block_ts, max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 930 u8 lms = 0; // Select AXI0 master for LLI fetching
94e13c28801677 Sia Jee Heng 2020-06-26 931 u32 offset;
94e13c28801677 Sia Jee Heng 2020-06-26 932
94e13c28801677 Sia Jee Heng 2020-06-26 933 if (unlikely(!is_slave_direction(direction)))
94e13c28801677 Sia Jee Heng 2020-06-26 934 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 935
94e13c28801677 Sia Jee Heng 2020-06-26 936 chan->direction = direction;
94e13c28801677 Sia Jee Heng 2020-06-26 937 chan->cyclic = 0x1;
94e13c28801677 Sia Jee Heng 2020-06-26 938
94e13c28801677 Sia Jee Heng 2020-06-26 939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
94e13c28801677 Sia Jee Heng 2020-06-26 940
94e13c28801677 Sia Jee Heng 2020-06-26 941 axi_set_hw_channel(chan->chip, chan->hw_hs_num);
94e13c28801677 Sia Jee Heng 2020-06-26 942
94e13c28801677 Sia Jee Heng 2020-06-26 943 switch (direction) {
94e13c28801677 Sia Jee Heng 2020-06-26 944 case DMA_MEM_TO_DEV:
94e13c28801677 Sia Jee Heng 2020-06-26 945 reg_width = __ffs(chan->slave_config.dst_addr_width);
94e13c28801677 Sia Jee Heng 2020-06-26 946
94e13c28801677 Sia Jee Heng 2020-06-26 947 chan->reg_width = reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
94e13c28801677 Sia Jee Heng 2020-06-26 949 offset = DMAC_APB_HALFWORD_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 950 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 951 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 952 axi_dma_apb_iowrite32(chan->chip,
94e13c28801677 Sia Jee Heng 2020-06-26 953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
94e13c28801677 Sia Jee Heng 2020-06-26 955 offset = DMAC_APB_BYTE_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 956 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 957 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 959 }
94e13c28801677 Sia Jee Heng 2020-06-26 960 reg = chan->slave_config.dst_addr;
94e13c28801677 Sia Jee Heng 2020-06-26 961
94e13c28801677 Sia Jee Heng 2020-06-26 962 ctllo = axi_dma_prepare_ctllo(chan) |
94e13c28801677 Sia Jee Heng 2020-06-26 963 reg_width << CH_CTL_L_DST_WIDTH_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 966
94e13c28801677 Sia Jee Heng 2020-06-26 967 for (i = 0; i < buf_len / period_len; i++) {
94e13c28801677 Sia Jee Heng 2020-06-26 968 struct axi_dma_desc *desc;
94e13c28801677 Sia Jee Heng 2020-06-26 969 size_t xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 970 u32 mem, len;
94e13c28801677 Sia Jee Heng 2020-06-26 971
94e13c28801677 Sia Jee Heng 2020-06-26 @972 mem_width = __ffs(data_width | mem | len);
^^^^^^^^^
Uninitialized variables.
94e13c28801677 Sia Jee Heng 2020-06-26 973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 974 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 975
94e13c28801677 Sia Jee Heng 2020-06-26 976 xfer_len = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 977 block_ts = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 978
94e13c28801677 Sia Jee Heng 2020-06-26 979 desc = axi_desc_get(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 980 if (unlikely(!desc))
94e13c28801677 Sia Jee Heng 2020-06-26 981 goto err_desc_get;
94e13c28801677 Sia Jee Heng 2020-06-26 982
94e13c28801677 Sia Jee Heng 2020-06-26 983 if (block_ts > max_block_ts) {
94e13c28801677 Sia Jee Heng 2020-06-26 984 block_ts = max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 985 xfer_len = max_block_ts << mem_width;
94e13c28801677 Sia Jee Heng 2020-06-26 986 }
94e13c28801677 Sia Jee Heng 2020-06-26 987
94e13c28801677 Sia Jee Heng 2020-06-26 988 ctlhi = axi_dma_prepare_ctlhi(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 989
94e13c28801677 Sia Jee Heng 2020-06-26 990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 991 write_desc_sar(desc, buf_addr + i * period_len);
94e13c28801677 Sia Jee Heng 2020-06-26 992 write_desc_dar(desc, reg);
94e13c28801677 Sia Jee Heng 2020-06-26 993 desc->lli.block_ts_lo = period_len / 4;
94e13c28801677 Sia Jee Heng 2020-06-26 994 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
94e13c28801677 Sia Jee Heng 2020-06-26 995 desc->lli.ctl_lo = cpu_to_le32(ctllo);
94e13c28801677 Sia Jee Heng 2020-06-26 996
94e13c28801677 Sia Jee Heng 2020-06-26 997 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 998 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 999
94e13c28801677 Sia Jee Heng 2020-06-26 1000 // Manage transfer list (xfer_list)
94e13c28801677 Sia Jee Heng 2020-06-26 1001 if (!first) {
94e13c28801677 Sia Jee Heng 2020-06-26 1002 first = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1003 } else {
94e13c28801677 Sia Jee Heng 2020-06-26 1004 write_desc_llp(prev, desc->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1005 list_add_tail(&desc->xfer_list,
94e13c28801677 Sia Jee Heng 2020-06-26 1006 &first->xfer_list);
94e13c28801677 Sia Jee Heng 2020-06-26 1007 }
94e13c28801677 Sia Jee Heng 2020-06-26 1008 prev = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1009 if (i == ((buf_len / period_len) - 1))
94e13c28801677 Sia Jee Heng 2020-06-26 1010 write_desc_llp(prev, first->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1011
94e13c28801677 Sia Jee Heng 2020-06-26 1012 total_len += xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1013
94e13c28801677 Sia Jee Heng 2020-06-26 1014 set_desc_last(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1015 }
94e13c28801677 Sia Jee Heng 2020-06-26 1016 break;
94e13c28801677 Sia Jee Heng 2020-06-26 1017 case DMA_DEV_TO_MEM:
94e13c28801677 Sia Jee Heng 2020-06-26 1018 reg_width = __ffs(chan->slave_config.src_addr_width);
94e13c28801677 Sia Jee Heng 2020-06-26 1019
94e13c28801677 Sia Jee Heng 2020-06-26 1020 chan->reg_width = reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
94e13c28801677 Sia Jee Heng 2020-06-26 1022 offset = DMAC_APB_HALFWORD_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 1024 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
94e13c28801677 Sia Jee Heng 2020-06-26 1027 offset = DMAC_APB_BYTE_WR_CH_EN;
94e13c28801677 Sia Jee Heng 2020-06-26 1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset);
94e13c28801677 Sia Jee Heng 2020-06-26 1029 reg_value |= 0x1 << chan->id;
94e13c28801677 Sia Jee Heng 2020-06-26 1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value);
94e13c28801677 Sia Jee Heng 2020-06-26 1031 }
94e13c28801677 Sia Jee Heng 2020-06-26 1032 reg = chan->slave_config.src_addr;
94e13c28801677 Sia Jee Heng 2020-06-26 1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 1035 ctllo = axi_dma_prepare_ctllo(chan) |
94e13c28801677 Sia Jee Heng 2020-06-26 1036 reg_width << CH_CTL_L_SRC_WIDTH_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
94e13c28801677 Sia Jee Heng 2020-06-26 1038 // Workaround
94e13c28801677 Sia Jee Heng 2020-06-26 1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 1040
94e13c28801677 Sia Jee Heng 2020-06-26 1041 for (i = 0; i < buf_len / period_len; i++) {
94e13c28801677 Sia Jee Heng 2020-06-26 1042 struct axi_dma_desc *desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1043 size_t xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1044 u32 mem, len;
94e13c28801677 Sia Jee Heng 2020-06-26 1045
94e13c28801677 Sia Jee Heng 2020-06-26 1046 desc = axi_desc_get(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 1047 if (unlikely(!desc))
94e13c28801677 Sia Jee Heng 2020-06-26 1048 goto err_desc_get;
94e13c28801677 Sia Jee Heng 2020-06-26 1049
94e13c28801677 Sia Jee Heng 2020-06-26 1050 xfer_len = len;
94e13c28801677 Sia Jee Heng 2020-06-26 1051 block_ts = xfer_len >> reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1052 if (block_ts > max_block_ts) {
94e13c28801677 Sia Jee Heng 2020-06-26 1053 block_ts = max_block_ts;
94e13c28801677 Sia Jee Heng 2020-06-26 1054 xfer_len = max_block_ts << reg_width;
94e13c28801677 Sia Jee Heng 2020-06-26 1055 }
94e13c28801677 Sia Jee Heng 2020-06-26 1056 xfer_len = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1057 block_ts = period_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1058 mem_width = __ffs(data_width | mem | xfer_len);
94e13c28801677 Sia Jee Heng 2020-06-26 1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
94e13c28801677 Sia Jee Heng 2020-06-26 1061
94e13c28801677 Sia Jee Heng 2020-06-26 1062 ctlhi = axi_dma_prepare_ctlhi(chan);
94e13c28801677 Sia Jee Heng 2020-06-26 1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS;
94e13c28801677 Sia Jee Heng 2020-06-26 1064
94e13c28801677 Sia Jee Heng 2020-06-26 1065 write_desc_sar(desc, reg);
94e13c28801677 Sia Jee Heng 2020-06-26 1066 write_desc_dar(desc, buf_addr + i * period_len);
94e13c28801677 Sia Jee Heng 2020-06-26 1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
94e13c28801677 Sia Jee Heng 2020-06-26 1068 desc->lli.block_ts_lo = period_len / 2;
94e13c28801677 Sia Jee Heng 2020-06-26 1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32)
94e13c28801677 Sia Jee Heng 2020-06-26 1070 desc->lli.block_ts_lo = period_len / 4;
94e13c28801677 Sia Jee Heng 2020-06-26 1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi);
94e13c28801677 Sia Jee Heng 2020-06-26 1072 desc->lli.ctl_lo = cpu_to_le32(ctllo);
94e13c28801677 Sia Jee Heng 2020-06-26 1073
94e13c28801677 Sia Jee Heng 2020-06-26 1074 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1075 set_desc_src_master(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1076
94e13c28801677 Sia Jee Heng 2020-06-26 1077 // Manage transfer list (xfer_list)
94e13c28801677 Sia Jee Heng 2020-06-26 1078 if (!first) {
94e13c28801677 Sia Jee Heng 2020-06-26 1079 first = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1080 } else {
94e13c28801677 Sia Jee Heng 2020-06-26 1081 write_desc_llp(prev, desc->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1082 list_add_tail(&desc->xfer_list,
94e13c28801677 Sia Jee Heng 2020-06-26 1083 &first->xfer_list);
94e13c28801677 Sia Jee Heng 2020-06-26 1084 }
94e13c28801677 Sia Jee Heng 2020-06-26 1085 prev = desc;
94e13c28801677 Sia Jee Heng 2020-06-26 1086 if (i == ((buf_len / period_len) - 1))
94e13c28801677 Sia Jee Heng 2020-06-26 1087 write_desc_llp(prev, first->vd.tx.phys | lms);
94e13c28801677 Sia Jee Heng 2020-06-26 1088
94e13c28801677 Sia Jee Heng 2020-06-26 1089 total_len += xfer_len;
94e13c28801677 Sia Jee Heng 2020-06-26 1090
94e13c28801677 Sia Jee Heng 2020-06-26 1091 // TODO: check if needed
94e13c28801677 Sia Jee Heng 2020-06-26 1092 set_desc_last(desc);
94e13c28801677 Sia Jee Heng 2020-06-26 1093 }
94e13c28801677 Sia Jee Heng 2020-06-26 1094 break;
94e13c28801677 Sia Jee Heng 2020-06-26 1095 default:
94e13c28801677 Sia Jee Heng 2020-06-26 1096 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1097 }
94e13c28801677 Sia Jee Heng 2020-06-26 1098
94e13c28801677 Sia Jee Heng 2020-06-26 1099 if (unlikely(!first))
94e13c28801677 Sia Jee Heng 2020-06-26 1100 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1101
94e13c28801677 Sia Jee Heng 2020-06-26 1102 return vchan_tx_prep(&chan->vc, &first->vd, flags);
94e13c28801677 Sia Jee Heng 2020-06-26 1103
94e13c28801677 Sia Jee Heng 2020-06-26 1104 err_desc_get:
94e13c28801677 Sia Jee Heng 2020-06-26 1105 if (first)
94e13c28801677 Sia Jee Heng 2020-06-26 1106 axi_desc_put(first);
94e13c28801677 Sia Jee Heng 2020-06-26 1107
94e13c28801677 Sia Jee Heng 2020-06-26 1108 return NULL;
94e13c28801677 Sia Jee Heng 2020-06-26 1109 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
1 year, 9 months
[intel-linux-intel-lts:5.4/yocto 39/1142] drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:941 axi_chan_handle_err() warn: inconsistent returns 'chan->vc.lock'.
by Dan Carpenter
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 2baf6e1cd6f179dd497cfc10294920e99bc3a66e [39/1142] dmaengine: dw-axi-dma: support slave dma mode
config: i386-randconfig-m021-20201209 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com>
smatch warnings:
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:941 axi_chan_handle_err() warn: inconsistent returns 'chan->vc.lock'.
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:941 axi_chan_handle_err() warn: inconsistent returns 'flags'.
vim +941 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 912
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 913 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 914 {
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 915 struct virt_dma_desc *vd;
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 916 unsigned long flags;
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 917
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 918 spin_lock_irqsave(&chan->vc.lock, flags);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 919
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 920 axi_chan_disable(chan);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 921
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 922 /* The bad descriptor currently is in the head of vc list */
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 923 vd = vchan_next_desc(&chan->vc);
2baf6e1cd6f179 Sia Jee Heng 2020-06-26 924 if (!vd)
2baf6e1cd6f179 Sia Jee Heng 2020-06-26 925 return;
^^^^^^^
spin_unlock_irqrestore(&chan->vc.lock, flags);
before returning.
2baf6e1cd6f179 Sia Jee Heng 2020-06-26 926
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 927 /* Remove the completed descriptor from issued list */
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 928 list_del(&vd->node);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 929
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 930 /* WARN about bad descriptor */
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 931 dev_err(chan2dev(chan),
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 932 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 933 axi_chan_name(chan), vd->tx.cookie, status);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 934 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 935
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 936 vchan_cookie_complete(vd);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 937
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 938 /* Try to restart the controller */
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 939 axi_chan_start_first_queued(chan);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 940
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 @941 spin_unlock_irqrestore(&chan->vc.lock, flags);
1fe20f1b84548b Eugeniy Paltsev 2018-03-06 942 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
1 year, 9 months
arch/arm64/kernel/entry-common.c:210:25: warning: no previous prototype for 'el0_sync_handler'
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2c85ebc57b3e1817b6ce1a6b703928e113a90442
commit: 582f95835a8fc812cd38dce0447fe9386b78913e arm64: entry: convert el0_sync to C
date: 1 year, 2 months ago
config: arm64-randconfig-r021-20201214 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit...
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 582f95835a8fc812cd38dce0447fe9386b78913e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
arch/arm64/kernel/entry-common.c:68:25: warning: no previous prototype for 'el1_sync_handler' [-Wmissing-prototypes]
68 | asmlinkage void notrace el1_sync_handler(struct pt_regs *regs)
| ^~~~~~~~~~~~~~~~
>> arch/arm64/kernel/entry-common.c:210:25: warning: no previous prototype for 'el0_sync_handler' [-Wmissing-prototypes]
210 | asmlinkage void notrace el0_sync_handler(struct pt_regs *regs)
| ^~~~~~~~~~~~~~~~
>> arch/arm64/kernel/entry-common.c:276:25: warning: no previous prototype for 'el0_sync_compat_handler' [-Wmissing-prototypes]
276 | asmlinkage void notrace el0_sync_compat_handler(struct pt_regs *regs)
| ^~~~~~~~~~~~~~~~~~~~~~~
vim +/el0_sync_handler +210 arch/arm64/kernel/entry-common.c
209
> 210 asmlinkage void notrace el0_sync_handler(struct pt_regs *regs)
211 {
212 unsigned long esr = read_sysreg(esr_el1);
213
214 switch (ESR_ELx_EC(esr)) {
215 case ESR_ELx_EC_SVC64:
216 el0_svc(regs);
217 break;
218 case ESR_ELx_EC_DABT_LOW:
219 el0_da(regs, esr);
220 break;
221 case ESR_ELx_EC_IABT_LOW:
222 el0_ia(regs, esr);
223 break;
224 case ESR_ELx_EC_FP_ASIMD:
225 el0_fpsimd_acc(regs, esr);
226 break;
227 case ESR_ELx_EC_SVE:
228 el0_sve_acc(regs, esr);
229 break;
230 case ESR_ELx_EC_FP_EXC64:
231 el0_fpsimd_exc(regs, esr);
232 break;
233 case ESR_ELx_EC_SYS64:
234 case ESR_ELx_EC_WFx:
235 el0_sys(regs, esr);
236 break;
237 case ESR_ELx_EC_SP_ALIGN:
238 el0_sp(regs, esr);
239 break;
240 case ESR_ELx_EC_PC_ALIGN:
241 el0_pc(regs, esr);
242 break;
243 case ESR_ELx_EC_UNKNOWN:
244 el0_undef(regs);
245 break;
246 case ESR_ELx_EC_BREAKPT_LOW:
247 case ESR_ELx_EC_SOFTSTP_LOW:
248 case ESR_ELx_EC_WATCHPT_LOW:
249 case ESR_ELx_EC_BRK64:
250 el0_dbg(regs, esr);
251 break;
252 default:
253 el0_inv(regs, esr);
254 }
255 }
256 NOKPROBE_SYMBOL(el0_sync_handler);
257
258 #ifdef CONFIG_COMPAT
259 static void notrace el0_cp15(struct pt_regs *regs, unsigned long esr)
260 {
261 user_exit_irqoff();
262 local_daif_restore(DAIF_PROCCTX);
263 do_cp15instr(esr, regs);
264 }
265 NOKPROBE_SYMBOL(el0_cp15);
266
267 static void notrace el0_svc_compat(struct pt_regs *regs)
268 {
269 if (system_uses_irq_prio_masking())
270 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
271
272 el0_svc_compat_handler(regs);
273 }
274 NOKPROBE_SYMBOL(el0_svc_compat);
275
> 276 asmlinkage void notrace el0_sync_compat_handler(struct pt_regs *regs)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
1 year, 9 months
[RFC PATCH] drm/i915: intel_detect_pch_virt() can be static
by kernel test robot
Reported-by: kernel test robot <lkp(a)intel.com>
Signed-off-by: kernel test robot <lkp(a)intel.com>
---
intel_pch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index ca5989700ecf23..a3f84327535688 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -184,7 +184,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
return id;
}
-void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
+static void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
{
unsigned short id;
enum intel_pch pch_type;
1 year, 9 months
[vkoul-dmaengine:test_ti 37/75] drivers/dma/imx-dma.c:1048:20: warning: cast to smaller integer type 'enum imx_dma_type' from 'const void
by kernel test robot
Hi Fabio,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git test_ti
head: 5b65781d06ea90ef2f8e51a13352c43c3daa8cdc
commit: 0ab785c894e618587e83bb67e8a8e96649868ad1 [37/75] dmaengine: imx-dma: Remove unused .id_table
config: arm64-randconfig-r032-20201214 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project d38205144febf4dc42c9270c6aa3d978f1ef65e1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commi...
git remote add vkoul-dmaengine https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git
git fetch --no-tags vkoul-dmaengine test_ti
git checkout 0ab785c894e618587e83bb67e8a8e96649868ad1
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> drivers/dma/imx-dma.c:1048:20: warning: cast to smaller integer type 'enum imx_dma_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
imxdma->devtype = (enum imx_dma_type)of_device_get_match_data(&pdev->dev);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +1048 drivers/dma/imx-dma.c
1035
1036 static int __init imxdma_probe(struct platform_device *pdev)
1037 {
1038 struct imxdma_engine *imxdma;
1039 struct resource *res;
1040 int ret, i;
1041 int irq, irq_err;
1042
1043 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1044 if (!imxdma)
1045 return -ENOMEM;
1046
1047 imxdma->dev = &pdev->dev;
> 1048 imxdma->devtype = (enum imx_dma_type)of_device_get_match_data(&pdev->dev);
1049
1050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1051 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1052 if (IS_ERR(imxdma->base))
1053 return PTR_ERR(imxdma->base);
1054
1055 irq = platform_get_irq(pdev, 0);
1056 if (irq < 0)
1057 return irq;
1058
1059 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1060 if (IS_ERR(imxdma->dma_ipg))
1061 return PTR_ERR(imxdma->dma_ipg);
1062
1063 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1064 if (IS_ERR(imxdma->dma_ahb))
1065 return PTR_ERR(imxdma->dma_ahb);
1066
1067 ret = clk_prepare_enable(imxdma->dma_ipg);
1068 if (ret)
1069 return ret;
1070 ret = clk_prepare_enable(imxdma->dma_ahb);
1071 if (ret)
1072 goto disable_dma_ipg_clk;
1073
1074 /* reset DMA module */
1075 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1076
1077 if (is_imx1_dma(imxdma)) {
1078 ret = devm_request_irq(&pdev->dev, irq,
1079 dma_irq_handler, 0, "DMA", imxdma);
1080 if (ret) {
1081 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1082 goto disable_dma_ahb_clk;
1083 }
1084 imxdma->irq = irq;
1085
1086 irq_err = platform_get_irq(pdev, 1);
1087 if (irq_err < 0) {
1088 ret = irq_err;
1089 goto disable_dma_ahb_clk;
1090 }
1091
1092 ret = devm_request_irq(&pdev->dev, irq_err,
1093 imxdma_err_handler, 0, "DMA", imxdma);
1094 if (ret) {
1095 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1096 goto disable_dma_ahb_clk;
1097 }
1098 imxdma->irq_err = irq_err;
1099 }
1100
1101 /* enable DMA module */
1102 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1103
1104 /* clear all interrupts */
1105 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1106
1107 /* disable interrupts */
1108 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1109
1110 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1111
1112 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1113 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1114 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1115 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1116
1117 /* Initialize 2D global parameters */
1118 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1119 imxdma->slots_2d[i].count = 0;
1120
1121 spin_lock_init(&imxdma->lock);
1122
1123 /* Initialize channel parameters */
1124 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1125 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1126
1127 if (!is_imx1_dma(imxdma)) {
1128 ret = devm_request_irq(&pdev->dev, irq + i,
1129 dma_irq_handler, 0, "DMA", imxdma);
1130 if (ret) {
1131 dev_warn(imxdma->dev, "Can't register IRQ %d "
1132 "for DMA channel %d\n",
1133 irq + i, i);
1134 goto disable_dma_ahb_clk;
1135 }
1136
1137 imxdmac->irq = irq + i;
1138 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1139 }
1140
1141 imxdmac->imxdma = imxdma;
1142
1143 INIT_LIST_HEAD(&imxdmac->ld_queue);
1144 INIT_LIST_HEAD(&imxdmac->ld_free);
1145 INIT_LIST_HEAD(&imxdmac->ld_active);
1146
1147 tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
1148 imxdmac->chan.device = &imxdma->dma_device;
1149 dma_cookie_init(&imxdmac->chan);
1150 imxdmac->channel = i;
1151
1152 /* Add the channel to the DMAC list */
1153 list_add_tail(&imxdmac->chan.device_node,
1154 &imxdma->dma_device.channels);
1155 }
1156
1157 imxdma->dma_device.dev = &pdev->dev;
1158
1159 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1160 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1161 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1162 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1163 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1164 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1165 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1166 imxdma->dma_device.device_config = imxdma_config;
1167 imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1168 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1169
1170 platform_set_drvdata(pdev, imxdma);
1171
1172 imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
1173 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1174
1175 ret = dma_async_device_register(&imxdma->dma_device);
1176 if (ret) {
1177 dev_err(&pdev->dev, "unable to register\n");
1178 goto disable_dma_ahb_clk;
1179 }
1180
1181 if (pdev->dev.of_node) {
1182 ret = of_dma_controller_register(pdev->dev.of_node,
1183 imxdma_xlate, imxdma);
1184 if (ret) {
1185 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1186 goto err_of_dma_controller;
1187 }
1188 }
1189
1190 return 0;
1191
1192 err_of_dma_controller:
1193 dma_async_device_unregister(&imxdma->dma_device);
1194 disable_dma_ahb_clk:
1195 clk_disable_unprepare(imxdma->dma_ahb);
1196 disable_dma_ipg_clk:
1197 clk_disable_unprepare(imxdma->dma_ipg);
1198 return ret;
1199 }
1200
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
1 year, 9 months
[kbuild] Re: [RFC PATCH 2/2] overlayfs: propagate errors from upper to overlay sb in sync_fs
by Dan Carpenter
Hi Jeff,
url: https://github.com/0day-ci/linux/commits/Jeff-Layton/errseq-overlayfs-acc...
base: https://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git overlayfs-next
config: i386-randconfig-m021-20201213 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com>
smatch warnings:
fs/overlayfs/super.c:272 ovl_sync_fs() error: uninitialized symbol 'upper_sb'.
vim +/upper_sb +272 fs/overlayfs/super.c
e8d4bfe3a715372 Chengguang Xu 2017-11-29 260 /* Sync real dirty inodes in upper filesystem (if it exists) */
e593b2bf513dd4d Amir Goldstein 2017-01-23 261 static int ovl_sync_fs(struct super_block *sb, int wait)
e593b2bf513dd4d Amir Goldstein 2017-01-23 262 {
ad204488d3046b3 Miklos Szeredi 2017-11-10 263 struct ovl_fs *ofs = sb->s_fs_info;
e593b2bf513dd4d Amir Goldstein 2017-01-23 264 struct super_block *upper_sb;
e593b2bf513dd4d Amir Goldstein 2017-01-23 265 int ret;
e593b2bf513dd4d Amir Goldstein 2017-01-23 266
08f4c7c86d4cf12 Miklos Szeredi 2020-06-04 267 if (!ovl_upper_mnt(ofs))
e593b2bf513dd4d Amir Goldstein 2017-01-23 268 return 0;
e8d4bfe3a715372 Chengguang Xu 2017-11-29 269
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 270 if (!ovl_should_sync(ofs)) {
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 271 /* Propagate errors from upper to overlayfs */
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 @272 ret = errseq_check(&upper_sb->s_wb_err, ofs->err_mark);
^^^^^^^^^^^^^^^^^^^
Uninitialized.
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 273 errseq_set(&sb->s_wb_err, ret);
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 274 return ret;
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 275 }
89bd90a6b2a9bc4 Jeff Layton 2020-12-13 276
e8d4bfe3a715372 Chengguang Xu 2017-11-29 277 /*
32b1924b210a70d Konstantin Khlebnikov 2020-04-09 278 * Not called for sync(2) call or an emergency sync (SB_I_SKIP_SYNC).
32b1924b210a70d Konstantin Khlebnikov 2020-04-09 279 * All the super blocks will be iterated, including upper_sb.
e8d4bfe3a715372 Chengguang Xu 2017-11-29 280 *
e8d4bfe3a715372 Chengguang Xu 2017-11-29 281 * If this is a syncfs(2) call, then we do need to call
e8d4bfe3a715372 Chengguang Xu 2017-11-29 282 * sync_filesystem() on upper_sb, but enough if we do it when being
e8d4bfe3a715372 Chengguang Xu 2017-11-29 283 * called with wait == 1.
e8d4bfe3a715372 Chengguang Xu 2017-11-29 284 */
e8d4bfe3a715372 Chengguang Xu 2017-11-29 285 if (!wait)
e593b2bf513dd4d Amir Goldstein 2017-01-23 286 return 0;
e593b2bf513dd4d Amir Goldstein 2017-01-23 287
08f4c7c86d4cf12 Miklos Szeredi 2020-06-04 288 upper_sb = ovl_upper_mnt(ofs)->mnt_sb;
e8d4bfe3a715372 Chengguang Xu 2017-11-29 289
e593b2bf513dd4d Amir Goldstein 2017-01-23 290 down_read(&upper_sb->s_umount);
e8d4bfe3a715372 Chengguang Xu 2017-11-29 291 ret = sync_filesystem(upper_sb);
e593b2bf513dd4d Amir Goldstein 2017-01-23 292 up_read(&upper_sb->s_umount);
e8d4bfe3a715372 Chengguang Xu 2017-11-29 293
e593b2bf513dd4d Amir Goldstein 2017-01-23 294 return ret;
e593b2bf513dd4d Amir Goldstein 2017-01-23 295 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
_______________________________________________
kbuild mailing list -- kbuild(a)lists.01.org
To unsubscribe send an email to kbuild-leave(a)lists.01.org
1 year, 9 months
Desinfetante
by Raquel Carvalho
Bom Dia,
A demanda por desinfetantes eficazes que permitam a eliminação de microrganismos prejudiciais é continuamente alta em todo o mundo.
Expandir a oferta com uma gama profissional de produtos com atividade viricida e bactericida permite aumentar a posição competitiva da empresa e construir novas redes de vendas.
Diversificamos a linha de atacadistas e distribuidores com sabonetes, líquidos e géis para desinfecção das mãos e outros produtos de limpeza, entre eles: géis de banho, shampoos e condicionadores de cabelo, além de detergentes concentrados.
Nossos parceiros de negócios estão aumentando sua participação no mercado externo devido à crescente satisfação do cliente e oferta diversificada.
O potencial de crescimento de nossas soluções resulta de preços acessíveis, alto desempenho e versatilidade para se adaptar a todos os tipos de pele.
A extensão da gama de produtos proposta é um campo interessante para a cooperação?
Cumprimentos,
Raquel Carvalho
Conselheiro do Cliente
1 year, 9 months