Re: [PATCH] fs: inode: use queue_rcu_work() instead of call_rcu()
by kernel test robot
Hi Zqiang,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.15-rc5 next-20211015]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zqiang/fs-inode-use-queue_rcu_wo...
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git ec681c53f8d2d0ee362ff67f5b98dd8263c15002
config: hexagon-randconfig-r041-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2294caaec521b45bdc9db96423fe51762...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zqiang/fs-inode-use-queue_rcu_work-instead-of-call_rcu/20211015-160455
git checkout 2294caaec521b45bdc9db96423fe51762e47afd0
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash fs/ntfs3/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>> fs/ntfs3/super.c:458:57: error: no member named 'i_rcu' in 'struct inode'
struct inode *inode = container_of(head, struct inode, i_rcu);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~
include/linux/kernel.h:495:53: note: expanded from macro 'container_of'
BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~
include/linux/compiler_types.h:264:74: note: expanded from macro '__same_type'
#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
^
include/linux/build_bug.h:39:58: note: expanded from macro 'BUILD_BUG_ON_MSG'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~
include/linux/compiler_types.h:322:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:310:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:302:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> fs/ntfs3/super.c:458:24: error: no member named 'i_rcu' in 'inode'
struct inode *inode = container_of(head, struct inode, i_rcu);
^ ~~~~~
include/linux/kernel.h:498:21: note: expanded from macro 'container_of'
((type *)(__mptr - offsetof(type, member))); })
^ ~~~~~~
include/linux/stddef.h:17:32: note: expanded from macro 'offsetof'
#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER)
^ ~~~~~~
include/linux/compiler_types.h:140:35: note: expanded from macro '__compiler_offsetof'
#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
^ ~
>> fs/ntfs3/super.c:458:16: error: initializing 'struct inode *' with an expression of incompatible type 'void'
struct inode *inode = container_of(head, struct inode, i_rcu);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
fs/ntfs3/super.c:468:19: error: no member named 'i_rcu' in 'struct inode'
call_rcu(&inode->i_rcu, ntfs_i_callback);
~~~~~ ^
4 errors generated.
vim +458 fs/ntfs3/super.c
82cae269cfa953 Konstantin Komarov 2021-08-13 455
82cae269cfa953 Konstantin Komarov 2021-08-13 456 static void ntfs_i_callback(struct rcu_head *head)
82cae269cfa953 Konstantin Komarov 2021-08-13 457 {
82cae269cfa953 Konstantin Komarov 2021-08-13 @458 struct inode *inode = container_of(head, struct inode, i_rcu);
82cae269cfa953 Konstantin Komarov 2021-08-13 459 struct ntfs_inode *ni = ntfs_i(inode);
82cae269cfa953 Konstantin Komarov 2021-08-13 460
82cae269cfa953 Konstantin Komarov 2021-08-13 461 mutex_destroy(&ni->ni_lock);
82cae269cfa953 Konstantin Komarov 2021-08-13 462
82cae269cfa953 Konstantin Komarov 2021-08-13 463 kmem_cache_free(ntfs_inode_cachep, ni);
82cae269cfa953 Konstantin Komarov 2021-08-13 464 }
82cae269cfa953 Konstantin Komarov 2021-08-13 465
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
by kernel test robot
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20211015]
[cannot apply to airlied/drm-next v5.15-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-...
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a005-20211014 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
437 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce lpt_pch_disable()
by kernel test robot
Hi Ville,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to airlied/drm-next v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Move-PCH-...
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a014-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7512167c38e587a77b2ea0f87e8c68fff...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Move-PCH-modeset-code-into-its-own-file/20211015-151850
git checkout 7512167c38e587a77b2ea0f87e8c68fff112804e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pch_display.c:437:6: warning: no previous prototype for function 'lpt_disable_pch_transcoder' [-Wmissing-prototypes]
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
drivers/gpu/drm/i915/display/intel_pch_display.c:437:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
^
static
1 warning generated.
vim +/lpt_disable_pch_transcoder +437 drivers/gpu/drm/i915/display/intel_pch_display.c
da423910ea9023 Ville Syrjälä 2021-10-15 436
da423910ea9023 Ville Syrjälä 2021-10-15 @437 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
da423910ea9023 Ville Syrjälä 2021-10-15 438 {
da423910ea9023 Ville Syrjälä 2021-10-15 439 u32 val;
da423910ea9023 Ville Syrjälä 2021-10-15 440
da423910ea9023 Ville Syrjälä 2021-10-15 441 val = intel_de_read(dev_priv, LPT_TRANSCONF);
da423910ea9023 Ville Syrjälä 2021-10-15 442 val &= ~TRANS_ENABLE;
da423910ea9023 Ville Syrjälä 2021-10-15 443 intel_de_write(dev_priv, LPT_TRANSCONF, val);
da423910ea9023 Ville Syrjälä 2021-10-15 444 /* wait for PCH transcoder off, transcoder state */
da423910ea9023 Ville Syrjälä 2021-10-15 445 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
da423910ea9023 Ville Syrjälä 2021-10-15 446 TRANS_STATE_ENABLE, 50))
da423910ea9023 Ville Syrjälä 2021-10-15 447 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
da423910ea9023 Ville Syrjälä 2021-10-15 448
da423910ea9023 Ville Syrjälä 2021-10-15 449 /* Workaround: clear timing override bit. */
da423910ea9023 Ville Syrjälä 2021-10-15 450 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
da423910ea9023 Ville Syrjälä 2021-10-15 451 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
da423910ea9023 Ville Syrjälä 2021-10-15 452 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
da423910ea9023 Ville Syrjälä 2021-10-15 453 }
da423910ea9023 Ville Syrjälä 2021-10-15 454
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[skeggsb:03.00-disp 44/65] drivers/gpu/drm/nouveau/dispnv50/disp.c:782:3: warning: variable 'config' is uninitialized when used here
by kernel test robot
tree: https://github.com/skeggsb/linux 03.00-disp
head: 9d141f4c5d74118aa6e66daa9fde389857627d89
commit: 6e294797f27c6dac80ca1f4acd046151056ecccf [44/65] drm/nouveau/disp: move HDMI config into acquire + infoframe methods
config: riscv-randconfig-r022-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/skeggsb/linux/commit/6e294797f27c6dac80ca1f4acd0461510...
git remote add skeggsb https://github.com/skeggsb/linux
git fetch --no-tags skeggsb 03.00-disp
git checkout 6e294797f27c6dac80ca1f4acd046151056ecccf
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/nouveau/dispnv50/disp.c:782:3: warning: variable 'config' is uninitialized when used here [-Wuninitialized]
config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
^~~~~~
drivers/gpu/drm/nouveau/dispnv50/disp.c:759:11: note: initialize the variable 'config' to silence this warning
u8 config, scdc = 0;
^
= '\0'
drivers/gpu/drm/nouveau/dispnv50/disp.c:2607:1: warning: no previous prototype for function 'nv50_display_create' [-Wmissing-prototypes]
nv50_display_create(struct drm_device *dev)
^
drivers/gpu/drm/nouveau/dispnv50/disp.c:2606:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int
^
static
2 warnings generated.
vim +/config +782 drivers/gpu/drm/nouveau/dispnv50/disp.c
78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 745
f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 746 /******************************************************************************
f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 747 * HDMI
f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 748 *****************************************************************************/
78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 749 static void
1b38cf6b03e92e drivers/gpu/drm/nouveau/dispnv50/disp.c Lyude Paul 2020-11-13 750 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
1b38cf6b03e92e drivers/gpu/drm/nouveau/dispnv50/disp.c Lyude Paul 2020-11-13 751 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 752 struct drm_display_mode *mode, bool hda)
78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 753 {
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 754 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 755 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 756 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 757 union hdmi_infoframe infoframe;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 758 const u8 rekey = 56; /* binary driver, and tegra, constant */
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 759 u8 config, scdc = 0;
64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 760 u32 max_ac_packet;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 761 struct {
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 762 struct nvif_outp_infoframe_v0 infoframe;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 763 u8 data[17];
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 764 } args;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 765 int ret, size;
34fd3e5d8c5f6b drivers/gpu/drm/nouveau/nv50_display.c Alastair Bridgewater 2017-04-11 766
64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 767 max_ac_packet = mode->htotal - mode->hdisplay;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 768 max_ac_packet -= rekey;
64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 769 max_ac_packet -= 18; /* constant from tegra */
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 770 max_ac_packet /= 32;
091e40cd952996 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 771
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 772 if (hdmi->scdc.scrambling.supported) {
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 773 const bool high_tmds_clock_ratio = mode->clock > 340000;
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 774
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 775
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 776 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 777 if (ret < 0) {
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 778 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 779 return;
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 780 }
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 781
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 @782 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 783 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 784 config |= SCDC_SCRAMBLING_ENABLE;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 785 if (high_tmds_clock_ratio)
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 786 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 787
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 788 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 789 if (ret < 0)
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 790 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 791 config, ret);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 792
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 793 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 794 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_SCRAMBLE;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 795 if (high_tmds_clock_ratio)
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 796 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_DIV_BY_4;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 797 }
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 798
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 799 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true,
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 800 max_ac_packet, rekey, scdc, hda);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 801 if (ret)
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 802 return;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 803
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 804 /* AVI InfoFrame. */
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 805 args.infoframe.version = 0;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 806 args.infoframe.head = nv_crtc->index;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 807
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 808 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode))
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 809 size = hdmi_infoframe_pack(&infoframe, args.data, 17);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 810 else
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 811 size = 0;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 812
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 813 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 814
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 815 /* Vendor InfoFrame. */
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 816 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 817 &nv_connector->base, mode))
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 818 size = hdmi_infoframe_pack(&infoframe, args.data, 17);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 819 else
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 820 size = 0;
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 821
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 822 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 823
6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 824 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 825 }
78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 826
:::::: The code at line 782 was first introduced by commit
:::::: 7a406f8a62ff0a3647f96f0cfdb518a99a01bf3f drm/nouveau/disp: add support for setting scdc parameters for high modes
:::::: TO: Ilia Mirkin <imirkin(a)alum.mit.edu>
:::::: CC: Ben Skeggs <bskeggs(a)redhat.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[tglx-devel:x86/fpu 81/82] ld: arch/x86/kernel/fpu/core.o:(__jump_table+0x44): undefined reference to `__fpu_state_size_dynamic'
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git x86/fpu
head: fbeb78415a1b32f890fa49e4355faa02bb0c0602
commit: 57e37526099d33c397f7a6bb1a0198ba1e148478 [81/82] x86/fpu: Add XFD handling for dynamic states
config: i386-buildonly-randconfig-r005-20211014 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/commit/?id...
git remote add tglx-devel https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
git fetch --no-tags tglx-devel x86/fpu
git checkout 57e37526099d33c397f7a6bb1a0198ba1e148478
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>> ld: arch/x86/kernel/fpu/core.o:(__jump_table+0x44): undefined reference to `__fpu_state_size_dynamic'
>> ld: arch/x86/kernel/fpu/xstate.o:(__jump_table+0x38): undefined reference to `__fpu_state_size_dynamic'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
Re: [PATCH] uapi: futex: Add a futex syscall
by kernel test robot
Hi Alistair,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linux/master]
[also build test WARNING on soc/for-next linus/master v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Alistair-Francis/uapi-futex-Add-...
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 5816b3e6577eaa676ceb00a848f0fd65fe2adc29
config: x86_64-randconfig-r015-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/38a003698424c55ceb42e9be69f47014a...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Alistair-Francis/uapi-futex-Add-a-futex-syscall/20211015-090054
git checkout 38a003698424c55ceb42e9be69f47014a6b4f6bd
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
In file included from <built-in>:1:
./usr/include/linux/futex_syscall.h:19:36: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
futex_syscall_timeout(__volatile__ u_int32_t *uaddr, int op, u_int32_t val,
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
./usr/include/linux/futex_syscall.h:19:62: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
futex_syscall_timeout(__volatile__ u_int32_t *uaddr, int op, u_int32_t val,
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
>> ./usr/include/linux/futex_syscall.h:20:16: warning: declaration of 'struct timespec' will not be visible outside of this function [-Wvisibility]
struct timespec *timeout, __volatile__ u_int32_t *uaddr2, int val3)
^
./usr/include/linux/futex_syscall.h:20:48: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
struct timespec *timeout, __volatile__ u_int32_t *uaddr2, int val3)
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
./usr/include/linux/futex_syscall.h:61:39: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
futex_syscall_nr_requeue(__volatile__ u_int32_t *uaddr, int op, u_int32_t val,
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
./usr/include/linux/futex_syscall.h:61:65: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
futex_syscall_nr_requeue(__volatile__ u_int32_t *uaddr, int op, u_int32_t val,
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
./usr/include/linux/futex_syscall.h:62:5: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
u_int32_t nr_requeue, __volatile__ u_int32_t *uaddr2, int val3)
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
./usr/include/linux/futex_syscall.h:62:40: error: unknown type name 'u_int32_t'; did you mean '__int128_t'?
u_int32_t nr_requeue, __volatile__ u_int32_t *uaddr2, int val3)
^~~~~~~~~
__int128_t
note: '__int128_t' declared here
1 warning and 7 errors generated.
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[tglx-devel:x86/fpu 81/82] core.c:undefined reference to `__fpu_state_size_dynamic'
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git x86/fpu
head: fbeb78415a1b32f890fa49e4355faa02bb0c0602
commit: 57e37526099d33c397f7a6bb1a0198ba1e148478 [81/82] x86/fpu: Add XFD handling for dynamic states
config: i386-tinyconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/commit/?id...
git remote add tglx-devel https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
git fetch --no-tags tglx-devel x86/fpu
git checkout 57e37526099d33c397f7a6bb1a0198ba1e148478
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
ld: arch/x86/kernel/fpu/core.o: in function `fpu_clone':
>> core.c:(.text+0x3ed): undefined reference to `__fpu_state_size_dynamic'
ld: arch/x86/kernel/fpu/xstate.o: in function `fpu__resume_cpu':
>> xstate.c:(.text+0x4af): undefined reference to `__fpu_state_size_dynamic'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[tglx-devel:x86/fpu 74/82] arch/x86/kernel/fpu/xstate.c:1314:21: sparse: sparse: incompatible types for operation (==):
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git x86/fpu
head: fbeb78415a1b32f890fa49e4355faa02bb0c0602
commit: 14b0c6c4efcd1654d291d501cca977f3476a5c10 [74/82] x86/fpu: Add sanity checks for XFD
config: x86_64-randconfig-s032-20211014 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/commit/?id...
git remote add tglx-devel https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
git fetch --no-tags tglx-devel x86/fpu
git checkout 14b0c6c4efcd1654d291d501cca977f3476a5c10
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=x86_64 SHELL=/bin/bash arch/x86/kernel/fpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
sparse warnings: (new ones prefixed by >>)
arch/x86/kernel/fpu/xstate.c:1353:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct lockdep_map const *lock @@ got struct lockdep_map [noderef] __rcu * @@
arch/x86/kernel/fpu/xstate.c:1353:9: sparse: expected struct lockdep_map const *lock
arch/x86/kernel/fpu/xstate.c:1353:9: sparse: got struct lockdep_map [noderef] __rcu *
arch/x86/kernel/fpu/xstate.c:1468:39: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
arch/x86/kernel/fpu/xstate.c:1468:39: sparse: expected struct spinlock [usertype] *lock
arch/x86/kernel/fpu/xstate.c:1468:39: sparse: got struct spinlock [noderef] __rcu *
arch/x86/kernel/fpu/xstate.c:1471:41: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
arch/x86/kernel/fpu/xstate.c:1471:41: sparse: expected struct spinlock [usertype] *lock
arch/x86/kernel/fpu/xstate.c:1471:41: sparse: got struct spinlock [noderef] __rcu *
>> arch/x86/kernel/fpu/xstate.c:1314:21: sparse: sparse: incompatible types for operation (==):
>> arch/x86/kernel/fpu/xstate.c:1314:21: sparse: struct fpstate *fpstate
>> arch/x86/kernel/fpu/xstate.c:1314:21: sparse: unsigned long long [usertype] xfd
vim +1314 arch/x86/kernel/fpu/xstate.c
1304
1305 #ifdef CONFIG_X86_DEBUG_FPU
1306 static inline bool xfd_valid(struct fpstate *fpstate, u64 mask, bool rstor)
1307 {
1308 u64 xfd = __this_cpu_read(xfd_state);
1309
1310 if (fpstate->xfd == xfd)
1311 return true;
1312
1313 /* For current's fpstate the XFD state must be correct. */
> 1314 if (fpstate == current->thread.fpu.fpstate->xfd)
1315 return false;
1316
1317 /*
1318 * XRSTOR(S) from init_fpstate are always correct as it will just
1319 * bring all components into init state and not read from the
1320 * buffer. XSAVE(S) raises #PF after init.
1321 */
1322 if (fpstate == &init_fpstate)
1323 return rstor;
1324
1325 /*
1326 * XSAVE(S): clone(), fpu_swap_kvm_fpu()
1327 * XRSTORS(S): fpu_swap_kvm_fpu()
1328 */
1329
1330 /* Remove XFD disabled states from the mask. */
1331 mask &= ~xfd;
1332 /* Remove features which are valid in fpstate. */
1333 mask &= ~fpstate->xfeatures;
1334
1335 /*
1336 * Mask should be zero now which means no loads/stores
1337 * past the end of the register state buffer.
1338 */
1339 return !mask;
1340 }
1341
1342 void xfd_validate_state(struct fpstate *fpstate, u64 mask, bool rstor)
1343 {
1344 WARN_ON_ONCE(!xfd_valid(fpstate, mask, rstor));
1345 }
1346 #endif /* CONFIG_X86_DEBUG_FPU */
1347
1348 static int validate_sigaltstack(unsigned int usize)
1349 {
1350 struct task_struct *thread, *leader = current->group_leader;
1351 unsigned long framesize = get_sigframe_size();
1352
> 1353 lockdep_assert_held(¤t->sighand->siglock);
1354
1355 /* get_sigframe_size() is based on fpu_user_cfg.max_size */
1356 framesize -= fpu_user_cfg.max_size;
1357 framesize += usize;
1358 for_each_thread(leader, thread) {
1359 if (thread->sas_ss_size && thread->sas_ss_size < framesize)
1360 return -ENOSPC;
1361 }
1362 return 0;
1363 }
1364
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[hch-misc:dax-block-cleanup 3/3] include/linux/dax.h:133:67: warning: declaration of 'struct gendisk' will not be visible outside of this function
by kernel test robot
tree: git://git.infradead.org/users/hch/misc.git dax-block-cleanup
head: f95e4c72e7784a68edcdb95f4211b9636880ff29
commit: f95e4c72e7784a68edcdb95f4211b9636880ff29 [3/3] dax: rework the dax_device <-> gendisk association
config: hexagon-randconfig-r041-20211014 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add hch-misc git://git.infradead.org/users/hch/misc.git
git fetch --no-tags hch-misc dax-block-cleanup
git checkout f95e4c72e7784a68edcdb95f4211b9636880ff29
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=hexagon
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
In file included from fs/erofs/super.c:14:
>> include/linux/dax.h:133:67: warning: declaration of 'struct gendisk' will not be visible outside of this function [-Wvisibility]
static inline int dax_add_host(struct dax_device *dax_dev, struct gendisk *disk)
^
include/linux/dax.h:137:29: warning: declaration of 'struct gendisk' will not be visible outside of this function [-Wvisibility]
void dax_remove_host(struct gendisk *disk)
^
>> include/linux/dax.h:137:6: warning: no previous prototype for function 'dax_remove_host' [-Wmissing-prototypes]
void dax_remove_host(struct gendisk *disk)
^
include/linux/dax.h:137:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void dax_remove_host(struct gendisk *disk)
^
static
3 warnings generated.
--
In file included from fs/erofs/data.c:9:
>> include/linux/dax.h:137:6: warning: no previous prototype for function 'dax_remove_host' [-Wmissing-prototypes]
void dax_remove_host(struct gendisk *disk)
^
include/linux/dax.h:137:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void dax_remove_host(struct gendisk *disk)
^
static
1 warning generated.
vim +133 include/linux/dax.h
123
124 struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev);
125 int dax_writeback_mapping_range(struct address_space *mapping,
126 struct dax_device *dax_dev, struct writeback_control *wbc);
127
128 struct page *dax_layout_busy_page(struct address_space *mapping);
129 struct page *dax_layout_busy_page_range(struct address_space *mapping, loff_t start, loff_t end);
130 dax_entry_t dax_lock_page(struct page *page);
131 void dax_unlock_page(struct page *page, dax_entry_t cookie);
132 #else
> 133 static inline int dax_add_host(struct dax_device *dax_dev, struct gendisk *disk)
134 {
135 return 0;
136 }
> 137 void dax_remove_host(struct gendisk *disk)
138 {
139 }
140 #define generic_fsdax_supported NULL
141
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
11 months, 1 week
- 1
- 0
[linux-next:master 5074/7806] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:42:20: error: no previous prototype for 'to_dal_irq_source_dcn201'
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 8006b911c90a4ec09958447d24c8a4c3538f5723
commit: 3f68c01be9a2227de1e190317fe34a6fb835a094 [5074/7806] drm/amd/display: add cyan_skillfish display support
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commi...
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout 3f68c01be9a2227de1e190317fe34a6fb835a094
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:42:20: error: no previous prototype for 'to_dal_irq_source_dcn201' [-Werror=missing-prototypes]
42 | enum dc_irq_source to_dal_irq_source_dcn201(
| ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:142:43: error: 'dmub_outbox_irq_info_funcs' defined but not used [-Werror=unused-const-variable=]
142 | static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:35:
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: error: 'UVD0_BASE' defined but not used [-Werror=unused-const-variable=]
129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: error: 'UMC0_BASE' defined but not used [-Werror=unused-const-variable=]
123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: error: 'THM_BASE' defined but not used [-Werror=unused-const-variable=]
117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: error: 'SMUIO_BASE' defined but not used [-Werror=unused-const-variable=]
111 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } },
| ^~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: error: 'OSSSYS_BASE' defined but not used [-Werror=unused-const-variable=]
105 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
| ^~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: error: 'NBIO_BASE' defined but not used [-Werror=unused-const-variable=]
99 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
| ^~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: error: 'MP1_BASE' defined but not used [-Werror=unused-const-variable=]
93 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: error: 'MP0_BASE' defined but not used [-Werror=unused-const-variable=]
87 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: error: 'MMHUB_BASE' defined but not used [-Werror=unused-const-variable=]
81 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
| ^~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: error: 'HDP_BASE' defined but not used [-Werror=unused-const-variable=]
75 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: error: 'GC_BASE' defined but not used [-Werror=unused-const-variable=]
69 | static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: error: 'FUSE_BASE' defined but not used [-Werror=unused-const-variable=]
63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } },
| ^~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: error: 'DMU_BASE' defined but not used [-Werror=unused-const-variable=]
57 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: error: 'DF_BASE' defined but not used [-Werror=unused-const-variable=]
51 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: error: 'CLK_BASE' defined but not used [-Werror=unused-const-variable=]
45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: error: 'ATHUB_BASE' defined but not used [-Werror=unused-const-variable=]
39 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
| ^~~~~~~~~~
cc1: all warnings being treated as errors
--
>> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:79:6: error: no previous prototype for 'dcn201_update_clocks_vbios' [-Werror=missing-prototypes]
79 | void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c: In function 'dcn201_update_clocks':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:134:7: error: variable 'enter_display_off' set but not used [-Werror=unused-but-set-variable]
134 | bool enter_display_off = false;
| ^~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:38:
At top level:
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: error: 'UVD0_BASE' defined but not used [-Werror=unused-const-variable=]
129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: error: 'UMC0_BASE' defined but not used [-Werror=unused-const-variable=]
123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: error: 'THM_BASE' defined but not used [-Werror=unused-const-variable=]
117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: error: 'SMUIO_BASE' defined but not used [-Werror=unused-const-variable=]
111 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } },
| ^~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: error: 'OSSSYS_BASE' defined but not used [-Werror=unused-const-variable=]
105 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
| ^~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: error: 'NBIO_BASE' defined but not used [-Werror=unused-const-variable=]
99 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
| ^~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: error: 'MP1_BASE' defined but not used [-Werror=unused-const-variable=]
93 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: error: 'MP0_BASE' defined but not used [-Werror=unused-const-variable=]
87 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: error: 'MMHUB_BASE' defined but not used [-Werror=unused-const-variable=]
81 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
| ^~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: error: 'HDP_BASE' defined but not used [-Werror=unused-const-variable=]
75 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: error: 'GC_BASE' defined but not used [-Werror=unused-const-variable=]
69 | static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: error: 'FUSE_BASE' defined but not used [-Werror=unused-const-variable=]
63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } },
| ^~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: error: 'DMU_BASE' defined but not used [-Werror=unused-const-variable=]
57 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: error: 'DF_BASE' defined but not used [-Werror=unused-const-variable=]
51 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: error: 'CLK_BASE' defined but not used [-Werror=unused-const-variable=]
45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
| ^~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: error: 'ATHUB_BASE' defined but not used [-Werror=unused-const-variable=]
39 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
| ^~~~~~~~~~
cc1: all warnings being treated as errors
--
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_init.c:127:6: error: no previous prototype for 'dcn201_hw_sequencer_construct' [-Werror=missing-prototypes]
127 | void dcn201_hw_sequencer_construct(struct dc *dc)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
--
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64:
>> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16515:111: error: initialized field overwritten [-Werror=override-init]
16515 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
365 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16515:111: note: (near initialization for 'aux_shift.AUX_SW_AUTOINCREMENT_DISABLE')
16515 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
365 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111: error: initialized field overwritten [-Werror=override-init]
16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
369 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111: note: (near initialization for 'aux_mask.AUX_SW_AUTOINCREMENT_DISABLE')
16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
369 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111: error: initialized field overwritten [-Werror=override-init]
17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:3: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111: note: (near initialization for 'le_shift.TMDS_CTL0')
17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:3: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111: error: initialized field overwritten [-Werror=override-init]
17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:3: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111: note: (near initialization for 'le_mask.TMDS_CTL0')
17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:3: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:61:
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[0].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[0].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[1].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[1].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[2].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[2].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[3].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error: initialized field overwritten [-Werror=override-init]
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[3].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: error: initialized field overwritten [-Werror=override-init]
5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:2: note: in expansion of macro 'TF_SF'
368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON'
547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: note: (near initialization for 'tf_shift.CM_3DLUT_MODE')
5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:2: note: in expansion of macro 'TF_SF'
368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON'
547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5183:111: error: initialized field overwritten [-Werror=override-init]
5183 | #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of macro 'CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:206:2: note: in expansion of macro 'TF_SF'
206 | TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:548:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_UPDATED'
548 | TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
..
vim +/to_dal_irq_source_dcn201 +42 drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c
41
> 42 enum dc_irq_source to_dal_irq_source_dcn201(
43 struct irq_service *irq_service,
44 uint32_t src_id,
45 uint32_t ext_id)
46 {
47 switch (src_id) {
48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK1;
50 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK2;
52 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
53 return DC_IRQ_SOURCE_DC1_VLINE0;
54 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
55 return DC_IRQ_SOURCE_DC2_VLINE0;
56 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
57 return DC_IRQ_SOURCE_PFLIP1;
58 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
59 return DC_IRQ_SOURCE_PFLIP2;
60 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
61 return DC_IRQ_SOURCE_VUPDATE1;
62 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
63 return DC_IRQ_SOURCE_VUPDATE2;
64 case DCN_1_0__SRCID__DC_HPD1_INT:
65 /* generic src_id for all HPD and HPDRX interrupts */
66 switch (ext_id) {
67 case DCN_1_0__CTXID__DC_HPD1_INT:
68 return DC_IRQ_SOURCE_HPD1;
69 case DCN_1_0__CTXID__DC_HPD2_INT:
70 return DC_IRQ_SOURCE_HPD2;
71 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
72 return DC_IRQ_SOURCE_HPD1RX;
73 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
74 return DC_IRQ_SOURCE_HPD2RX;
75 default:
76 return DC_IRQ_SOURCE_INVALID;
77 }
78 break;
79
80 default:
81 return DC_IRQ_SOURCE_INVALID;
82 }
83 return DC_IRQ_SOURCE_INVALID;
84 }
85
86 static bool hpd_ack(
87 struct irq_service *irq_service,
88 const struct irq_source_info *info)
89 {
90 uint32_t addr = info->status_reg;
91 uint32_t value = dm_read_reg(irq_service->ctx, addr);
92 uint32_t current_status =
93 get_reg_field_value(
94 value,
95 HPD0_DC_HPD_INT_STATUS,
96 DC_HPD_SENSE_DELAYED);
97
98 dal_irq_service_ack_generic(irq_service, info);
99
100 value = dm_read_reg(irq_service->ctx, info->enable_reg);
101
102 set_reg_field_value(
103 value,
104 current_status ? 0 : 1,
105 HPD0_DC_HPD_INT_CONTROL,
106 DC_HPD_INT_POLARITY);
107
108 dm_write_reg(irq_service->ctx, info->enable_reg, value);
109
110 return true;
111 }
112
113 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
114 .set = NULL,
115 .ack = hpd_ack
116 };
117
118 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
119 .set = NULL,
120 .ack = NULL
121 };
122
123 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
124 .set = NULL,
125 .ack = NULL
126 };
127
128 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
129 .set = NULL,
130 .ack = NULL
131 };
132
133 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
134 .set = NULL,
135 .ack = NULL
136 };
137 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
138 .set = NULL,
139 .ack = NULL
140 };
141
> 142 static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
143 .set = NULL,
144 .ack = NULL
145 };
146
---
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