[arm:zii 168/186] drivers/net/phy/phylink.c:2707:33: error: no member named 'sfp_link_an_mode' in 'struct phylink'; did you mean 'cfg_link_an_mode'?
by kernel test robot
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git zii
head: bc8489278c9545054f74b2226d3e2c09ec4e05fe
commit: efbf0d75c44bb5fb993fd90f03121a045abf2b77 [168/186] net: phylink: pass mode into phylink_validate()
config: i386-randconfig-a012-20211212 (https://download.01.org/0day-ci/archive/20211213/202112131514.7ATEatIp-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add arm git://git.armlinux.org.uk/~rmk/linux-arm.git
git fetch --no-tags arm zii
git checkout efbf0d75c44bb5fb993fd90f03121a045abf2b77
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/net/phy/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>> drivers/net/phy/phylink.c:2707:33: error: no member named 'sfp_link_an_mode' in 'struct phylink'; did you mean 'cfg_link_an_mode'?
ret = phylink_validate(pl, pl->sfp_link_an_mode, support, &config);
^~~~~~~~~~~~~~~~
cfg_link_an_mode
drivers/net/phy/phylink.c:55:5: note: 'cfg_link_an_mode' declared here
u8 cfg_link_an_mode; /* MLO_AN_xxx */
^
drivers/net/phy/phylink.c:2724:33: error: no member named 'sfp_link_an_mode' in 'struct phylink'; did you mean 'cfg_link_an_mode'?
ret = phylink_validate(pl, pl->sfp_link_an_mode, support1, &config);
^~~~~~~~~~~~~~~~
cfg_link_an_mode
drivers/net/phy/phylink.c:55:5: note: 'cfg_link_an_mode' declared here
u8 cfg_link_an_mode; /* MLO_AN_xxx */
^
2 errors generated.
vim +2707 drivers/net/phy/phylink.c
2684
2685 static int phylink_sfp_config(struct phylink *pl, u8 mode,
2686 const unsigned long *supported,
2687 const unsigned long *advertising)
2688 {
2689 __ETHTOOL_DECLARE_LINK_MODE_MASK(support1);
2690 __ETHTOOL_DECLARE_LINK_MODE_MASK(support);
2691 struct phylink_link_state config;
2692 phy_interface_t iface;
2693 bool changed;
2694 int ret;
2695
2696 linkmode_copy(support, supported);
2697
2698 memset(&config, 0, sizeof(config));
2699 linkmode_copy(config.advertising, advertising);
2700 config.interface = PHY_INTERFACE_MODE_NA;
2701 config.speed = SPEED_UNKNOWN;
2702 config.duplex = DUPLEX_UNKNOWN;
2703 config.pause = MLO_PAUSE_AN;
2704 config.an_enabled = pl->link_config.an_enabled;
2705
2706 /* Ignore errors if we're expecting a PHY to attach later */
> 2707 ret = phylink_validate(pl, pl->sfp_link_an_mode, support, &config);
2708 if (ret) {
2709 phylink_err(pl, "validation with support %*pb failed: %d\n",
2710 __ETHTOOL_LINK_MODE_MASK_NBITS, support, ret);
2711 return ret;
2712 }
2713
2714 iface = sfp_select_interface(pl->sfp_bus, config.advertising);
2715 if (iface == PHY_INTERFACE_MODE_NA) {
2716 phylink_err(pl,
2717 "selection of interface failed, advertisement %*pb\n",
2718 __ETHTOOL_LINK_MODE_MASK_NBITS, config.advertising);
2719 return -EINVAL;
2720 }
2721
2722 config.interface = iface;
2723 linkmode_copy(support1, support);
2724 ret = phylink_validate(pl, pl->sfp_link_an_mode, support1, &config);
2725 if (ret) {
2726 phylink_err(pl, "validation of %s/%s with support %*pb failed: %d\n",
2727 phylink_an_mode_str(mode),
2728 phy_modes(config.interface),
2729 __ETHTOOL_LINK_MODE_MASK_NBITS, support, ret);
2730 return ret;
2731 }
2732
2733 phylink_dbg(pl, "requesting link mode %s/%s with support %*pb\n",
2734 phylink_an_mode_str(mode), phy_modes(config.interface),
2735 __ETHTOOL_LINK_MODE_MASK_NBITS, support);
2736
2737 if (phy_interface_mode_is_8023z(iface) && pl->phydev)
2738 return -EINVAL;
2739
2740 changed = !linkmode_equal(pl->supported, support) ||
2741 !linkmode_equal(pl->link_config.advertising,
2742 config.advertising);
2743 if (changed) {
2744 linkmode_copy(pl->supported, support);
2745 linkmode_copy(pl->link_config.advertising, config.advertising);
2746 }
2747
2748 if (pl->cur_link_an_mode != mode ||
2749 pl->link_config.interface != config.interface) {
2750 pl->link_config.interface = config.interface;
2751 pl->cur_link_an_mode = mode;
2752
2753 changed = true;
2754
2755 phylink_info(pl, "switched to %s/%s link mode\n",
2756 phylink_an_mode_str(mode),
2757 phy_modes(config.interface));
2758 }
2759
2760 pl->link_port = pl->sfp_port;
2761
2762 if (changed && !test_bit(PHYLINK_DISABLE_STOPPED,
2763 &pl->phylink_disable_state))
2764 phylink_mac_initial_config(pl, false);
2765
2766 return ret;
2767 }
2768
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
drivers/watchdog/mtx-1_wdt.c:184:27: sparse: sparse: incorrect type in initializer (incompatible argument 2 (different address spaces))
by kernel test robot
Hi Randy,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 2585cf9dfaaddf00b069673f27bb3f8530e2039c
commit: 76215889be9d2cd388207545424bbbe3bf80e1ea watchdog: mtx-1: drop au1000.h header file
date: 6 months ago
config: mips-randconfig-s032-20211213 (https://download.01.org/0day-ci/archive/20211213/202112131443.4HWvLXx9-lk...)
compiler: mips64-linux-gcc (GCC) 11.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit...
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 76215889be9d2cd388207545424bbbe3bf80e1ea
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=mips SHELL=/bin/bash drivers/watchdog/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
sparse warnings: (new ones prefixed by >>)
command-line: note: in included file:
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQUIRE redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_SEQ_CST redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_ACQ_REL redefined
builtin:0:0: sparse: this was the original definition
builtin:1:9: sparse: sparse: preprocessor token __ATOMIC_RELEASE redefined
builtin:0:0: sparse: this was the original definition
>> drivers/watchdog/mtx-1_wdt.c:184:27: sparse: sparse: incorrect type in initializer (incompatible argument 2 (different address spaces)) @@ expected long ( *write )( ... ) @@ got long ( * )( ... ) @@
drivers/watchdog/mtx-1_wdt.c:184:27: sparse: expected long ( *write )( ... )
drivers/watchdog/mtx-1_wdt.c:184:27: sparse: got long ( * )( ... )
vim +184 drivers/watchdog/mtx-1_wdt.c
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 177
b47a166ed0baaa drivers/watchdog/mtx-1_wdt.c Jan Engelhardt 2008-01-22 178 static const struct file_operations mtx1_wdt_fops = {
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 179 .owner = THIS_MODULE,
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 180 .llseek = no_llseek,
ed78c2da149247 drivers/watchdog/mtx-1_wdt.c Alan Cox 2008-05-19 181 .unlocked_ioctl = mtx1_wdt_ioctl,
b6dfb2477fb0bf drivers/watchdog/mtx-1_wdt.c Arnd Bergmann 2019-06-03 182 .compat_ioctl = compat_ptr_ioctl,
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 183 .open = mtx1_wdt_open,
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 @184 .write = mtx1_wdt_write,
7944d3a5a70ee5 drivers/watchdog/mtx-1_wdt.c Wim Van Sebroeck 2008-08-06 185 .release = mtx1_wdt_release,
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 186 };
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 187
04bf3b4f5fc033 drivers/char/watchdog/mtx-1_wdt.c Florian Fainelli 2007-05-06 188
:::::: The code at line 184 was first introduced by commit
:::::: 04bf3b4f5fc033adf921f2e57d034ddbebef5fe7 [WATCHDOG] MTX-1 Watchdog driver
:::::: TO: Florian Fainelli <florian.fainelli(a)int-evry.fr>
:::::: CC: Wim Van Sebroeck <wim(a)iguana.be>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
[sashal-stable:pending-4.19 1/1] drivers/pinctrl/pinctrl-amd.c:966:2: error: implicit declaration of function 'acpi_register_wakeup_handler'; did you mean 'acpi_remove_gpe_handler'?
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git pending-4.19
head: a2dce07496954ec6f269d1ca5e1309e09c9283f5
commit: a2dce07496954ec6f269d1ca5e1309e09c9283f5 [1/1] pinctrl: amd: Fix wakeups when IRQ is shared with SCI
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20211213/202112131411.dlQkbktU-lk...)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git/c...
git remote add sashal-stable https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git
git fetch --no-tags sashal-stable pending-4.19
git checkout a2dce07496954ec6f269d1ca5e1309e09c9283f5
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/pinctrl/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_probe':
>> drivers/pinctrl/pinctrl-amd.c:966:2: error: implicit declaration of function 'acpi_register_wakeup_handler'; did you mean 'acpi_remove_gpe_handler'? [-Werror=implicit-function-declaration]
966 | acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
| acpi_remove_gpe_handler
drivers/pinctrl/pinctrl-amd.c:966:39: error: 'struct amd_gpio' has no member named 'irq'
966 | acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
| ^~
drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_remove':
>> drivers/pinctrl/pinctrl-amd.c:984:2: error: implicit declaration of function 'acpi_unregister_wakeup_handler' [-Werror=implicit-function-declaration]
984 | acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +966 drivers/pinctrl/pinctrl-amd.c
925
926 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
927 gpio_dev->groups = kerncz_groups;
928 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
929
930 amd_pinctrl_desc.name = dev_name(&pdev->dev);
931 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
932 gpio_dev);
933 if (IS_ERR(gpio_dev->pctrl)) {
934 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
935 return PTR_ERR(gpio_dev->pctrl);
936 }
937
938 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
939 if (ret)
940 return ret;
941
942 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
943 0, 0, gpio_dev->gc.ngpio);
944 if (ret) {
945 dev_err(&pdev->dev, "Failed to add pin range\n");
946 goto out2;
947 }
948
949 ret = gpiochip_irqchip_add(&gpio_dev->gc,
950 &amd_gpio_irqchip,
951 0,
952 handle_simple_irq,
953 IRQ_TYPE_NONE);
954 if (ret) {
955 dev_err(&pdev->dev, "could not add irqchip\n");
956 ret = -ENODEV;
957 goto out2;
958 }
959
960 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
961 KBUILD_MODNAME, gpio_dev);
962 if (ret)
963 goto out2;
964
965 platform_set_drvdata(pdev, gpio_dev);
> 966 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
967
968 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
969 return ret;
970
971 out2:
972 gpiochip_remove(&gpio_dev->gc);
973
974 return ret;
975 }
976
977 static int amd_gpio_remove(struct platform_device *pdev)
978 {
979 struct amd_gpio *gpio_dev;
980
981 gpio_dev = platform_get_drvdata(pdev);
982
983 gpiochip_remove(&gpio_dev->gc);
> 984 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
985
986 return 0;
987 }
988
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
Re: [PATCH v2 1/2] drm/msm/a5xx: Add support for Adreno 506 GPU
by kernel test robot
Hi Vladimir,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v5.16-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vladimir-Lypak/drm-msm-a5xx-Add-...
base: git://anongit.freedesktop.org/drm/drm drm-next
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20211213/202112131430.xn9Z7DDL-lk...)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8b3d7b1aee7cbef05b8df99a0d17e1da5...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vladimir-Lypak/drm-msm-a5xx-Add-support-for-Adreno-506-GPU/20211213-004110
git checkout 8b3d7b1aee7cbef05b8df99a0d17e1da59b23752
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Note: the linux-review/Vladimir-Lypak/drm-msm-a5xx-Add-support-for-Adreno-506-GPU/20211213-004110 HEAD 9035efa0597803896493d62ee3a5e1d34e0ab080 builds fine.
It only hurts bisectability.
All errors (new ones prefixed by >>):
drivers/gpu/drm/msm/adreno/a5xx_gpu.c: In function 'a5xx_hw_init':
>> drivers/gpu/drm/msm/adreno/a5xx_gpu.c:863:28: error: 'adreno_gou' undeclared (first use in this function); did you mean 'adreno_gpu'?
863 | if (adreno_is_a506(adreno_gou) || adreno_is_a508(adreno_gpu) ||
| ^~~~~~~~~~
| adreno_gpu
drivers/gpu/drm/msm/adreno/a5xx_gpu.c:863:28: note: each undeclared identifier is reported only once for each function it appears in
vim +863 drivers/gpu/drm/msm/adreno/a5xx_gpu.c
658
659 #define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \
660 A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \
661 A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \
662 A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT | \
663 A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \
664 A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \
665 A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
666 A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT | \
667 A5XX_RBBM_INT_0_MASK_CP_SW | \
668 A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
669 A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
670 A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP)
671
672 static int a5xx_hw_init(struct msm_gpu *gpu)
673 {
674 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
675 struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
676 u32 regbit;
677 int ret;
678
679 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
680
681 if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
682 adreno_is_a540(adreno_gpu))
683 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
684
685 /* Make all blocks contribute to the GPU BUSY perf counter */
686 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF);
687
688 /* Enable RBBM error reporting bits */
689 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001);
690
691 if (adreno_gpu->info->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) {
692 /*
693 * Mask out the activity signals from RB1-3 to avoid false
694 * positives
695 */
696
697 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11,
698 0xF0000000);
699 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12,
700 0xFFFFFFFF);
701 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13,
702 0xFFFFFFFF);
703 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14,
704 0xFFFFFFFF);
705 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15,
706 0xFFFFFFFF);
707 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16,
708 0xFFFFFFFF);
709 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17,
710 0xFFFFFFFF);
711 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18,
712 0xFFFFFFFF);
713 }
714
715 /* Enable fault detection */
716 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL,
717 (1 << 30) | 0xFFFF);
718
719 /* Turn on performance counters */
720 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01);
721
722 /* Select CP0 to always count cycles */
723 gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
724
725 /* Select RBBM0 to countable 6 to get the busy status for devfreq */
726 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6);
727
728 /* Increase VFD cache access so LRZ and other data gets evicted less */
729 gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);
730
731 /* Disable L2 bypass in the UCHE */
732 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000);
733 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF);
734 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000);
735 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF);
736
737 /* Set the GMEM VA range (0 to gpu->gmem) */
738 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
739 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
740 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
741 0x00100000 + adreno_gpu->gmem - 1);
742 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
743
744 if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
745 adreno_is_a510(adreno_gpu)) {
746 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
747 if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
748 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
749 else
750 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
751 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
752 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
753 } else {
754 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
755 if (adreno_is_a530(adreno_gpu))
756 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
757 else
758 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
759 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
760 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
761 }
762
763 if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
764 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
765 (0x100 << 11 | 0x100 << 22));
766 else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
767 adreno_is_a512(adreno_gpu))
768 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
769 (0x200 << 11 | 0x200 << 22));
770 else
771 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
772 (0x400 << 11 | 0x300 << 22));
773
774 if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
775 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
776
777 /*
778 * Disable the RB sampler datapath DP2 clock gating optimization
779 * for 1-SP GPUs, as it is enabled by default.
780 */
781 if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
782 adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
783 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
784
785 /* Disable UCHE global filter as SP can invalidate/flush independently */
786 gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29));
787
788 /* Enable USE_RETENTION_FLOPS */
789 gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
790
791 /* Enable ME/PFP split notification */
792 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF);
793
794 /*
795 * In A5x, CCU can send context_done event of a particular context to
796 * UCHE which ultimately reaches CP even when there is valid
797 * transaction of that context inside CCU. This can let CP to program
798 * config registers, which will make the "valid transaction" inside
799 * CCU to be interpreted differently. This can cause gpu fault. This
800 * bug is fixed in latest A510 revision. To enable this bug fix -
801 * bit[11] of RB_DBG_ECO_CNTL need to be set to 0, default is 1
802 * (disable). For older A510 version this bit is unused.
803 */
804 if (adreno_is_a510(adreno_gpu))
805 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0);
806
807 /* Enable HWCG */
808 a5xx_set_hwcg(gpu, true);
809
810 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
811
812 /* Set the highest bank bit */
813 if (adreno_is_a540(adreno_gpu))
814 regbit = 2;
815 else
816 regbit = 1;
817
818 gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7);
819 gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1);
820
821 if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
822 adreno_is_a540(adreno_gpu))
823 gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit);
824
825 /* Disable All flat shading optimization (ALLFLATOPTDIS) */
826 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10));
827
828 /* Protect registers from the CP */
829 gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
830
831 /* RBBM */
832 gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4));
833 gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8));
834 gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16));
835 gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32));
836 gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64));
837 gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64));
838
839 /* Content protect */
840 gpu_write(gpu, REG_A5XX_CP_PROTECT(6),
841 ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
842 16));
843 gpu_write(gpu, REG_A5XX_CP_PROTECT(7),
844 ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TRUST_CNTL, 2));
845
846 /* CP */
847 gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64));
848 gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8));
849 gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32));
850 gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1));
851
852 /* RB */
853 gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1));
854 gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2));
855
856 /* VPC */
857 gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8));
858 gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16));
859
860 /* UCHE */
861 gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
862
> 863 if (adreno_is_a506(adreno_gou) || adreno_is_a508(adreno_gpu) ||
864 adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
865 adreno_is_a512(adreno_gpu) || adreno_is_a530(adreno_gpu))
866 gpu_write(gpu, REG_A5XX_CP_PROTECT(17),
867 ADRENO_PROTECT_RW(0x10000, 0x8000));
868
869 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0);
870 /*
871 * Disable the trusted memory range - we don't actually supported secure
872 * memory rendering at this point in time and we don't want to block off
873 * part of the virtual memory space.
874 */
875 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
876 REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
877 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
878
879 /* Put the GPU into 64 bit by default */
880 gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);
881 gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);
882 gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);
883 gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);
884 gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);
885 gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);
886 gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);
887 gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);
888 gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);
889 gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);
890 gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
891 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
892
893 /*
894 * VPC corner case with local memory load kill leads to corrupt
895 * internal state. Normal Disable does not work for all a5x chips.
896 * So do the following setting to disable it.
897 */
898 if (adreno_gpu->info->quirks & ADRENO_QUIRK_LMLOADKILL_DISABLE) {
899 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23));
900 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0);
901 }
902
903 ret = adreno_hw_init(gpu);
904 if (ret)
905 return ret;
906
907 if (adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))
908 a5xx_gpmu_ucode_init(gpu);
909
910 ret = a5xx_ucode_init(gpu);
911 if (ret)
912 return ret;
913
914 /* Set the ringbuffer address */
915 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,
916 gpu->rb[0]->iova);
917
918 /*
919 * If the microcode supports the WHERE_AM_I opcode then we can use that
920 * in lieu of the RPTR shadow and enable preemption. Otherwise, we
921 * can't safely use the RPTR shadow or preemption. In either case, the
922 * RPTR shadow should be disabled in hardware.
923 */
924 gpu_write(gpu, REG_A5XX_CP_RB_CNTL,
925 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
926
927 /* Create a privileged buffer for the RPTR shadow */
928 if (a5xx_gpu->has_whereami) {
929 if (!a5xx_gpu->shadow_bo) {
930 a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
931 sizeof(u32) * gpu->nr_rings,
932 MSM_BO_WC | MSM_BO_MAP_PRIV,
933 gpu->aspace, &a5xx_gpu->shadow_bo,
934 &a5xx_gpu->shadow_iova);
935
936 if (IS_ERR(a5xx_gpu->shadow))
937 return PTR_ERR(a5xx_gpu->shadow);
938 }
939
940 gpu_write64(gpu, REG_A5XX_CP_RB_RPTR_ADDR,
941 REG_A5XX_CP_RB_RPTR_ADDR_HI, shadowptr(a5xx_gpu, gpu->rb[0]));
942 } else if (gpu->nr_rings > 1) {
943 /* Disable preemption if WHERE_AM_I isn't available */
944 a5xx_preempt_fini(gpu);
945 gpu->nr_rings = 1;
946 }
947
948 a5xx_preempt_hw_init(gpu);
949
950 /* Disable the interrupts through the initial bringup stage */
951 gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
952
953 /* Clear ME_HALT to start the micro engine */
954 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0);
955 ret = a5xx_me_init(gpu);
956 if (ret)
957 return ret;
958
959 ret = a5xx_power_init(gpu);
960 if (ret)
961 return ret;
962
963 /*
964 * Send a pipeline event stat to get misbehaving counters to start
965 * ticking correctly
966 */
967 if (adreno_is_a530(adreno_gpu)) {
968 OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1);
969 OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT));
970
971 a5xx_flush(gpu, gpu->rb[0], true);
972 if (!a5xx_idle(gpu, gpu->rb[0]))
973 return -EINVAL;
974 }
975
976 /*
977 * If the chip that we are using does support loading one, then
978 * try to load a zap shader into the secure world. If successful
979 * we can use the CP to switch out of secure mode. If not then we
980 * have no resource but to try to switch ourselves out manually. If we
981 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
982 * be blocked and a permissions violation will soon follow.
983 */
984 ret = a5xx_zap_shader_init(gpu);
985 if (!ret) {
986 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
987 OUT_RING(gpu->rb[0], 0x00000000);
988
989 a5xx_flush(gpu, gpu->rb[0], true);
990 if (!a5xx_idle(gpu, gpu->rb[0]))
991 return -EINVAL;
992 } else if (ret == -ENODEV) {
993 /*
994 * This device does not use zap shader (but print a warning
995 * just in case someone got their dt wrong.. hopefully they
996 * have a debug UART to realize the error of their ways...
997 * if you mess this up you are about to crash horribly)
998 */
999 dev_warn_once(gpu->dev->dev,
1000 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
1001 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1002 } else {
1003 return ret;
1004 }
1005
1006 /* Last step - yield the ringbuffer */
1007 a5xx_preempt_start(gpu);
1008
1009 return 0;
1010 }
1011
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
Re: [PATCH v4 08/14] ACPI: add perf low power callback
by kernel test robot
Hi Stephane,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/perf/core]
[also build test ERROR on tip/x86/core v5.16-rc5]
[cannot apply to rafael-pm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-x86-amd-Ad...
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git a9f4a6e92b3b319296fb078da2615f618f6cd80c
config: i386-randconfig-a013-20211210 (https://download.01.org/0day-ci/archive/20211213/202112131356.nvv2mpcK-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9d928356688ed9c42e01fed16e59c1d6e...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Stephane-Eranian/perf-x86-amd-Add-AMD-Fam19h-Branch-Sampling-support/20211211-050541
git checkout 9d928356688ed9c42e01fed16e59c1d6eda16647
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/acpi/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>> drivers/acpi/acpi_pad.c:168:4: error: implicit declaration of function 'perf_lopwr_cb' [-Werror,-Wimplicit-function-declaration]
perf_lopwr_cb(true);
^
1 error generated.
vim +/perf_lopwr_cb +168 drivers/acpi/acpi_pad.c
135
136 static unsigned int idle_pct = 5; /* percentage */
137 static unsigned int round_robin_time = 1; /* second */
138 static int power_saving_thread(void *data)
139 {
140 int do_sleep;
141 unsigned int tsk_index = (unsigned long)data;
142 u64 last_jiffies = 0;
143
144 sched_set_fifo_low(current);
145
146 while (!kthread_should_stop()) {
147 unsigned long expire_time;
148
149 /* round robin to cpus */
150 expire_time = last_jiffies + round_robin_time * HZ;
151 if (time_before(expire_time, jiffies)) {
152 last_jiffies = jiffies;
153 round_robin_cpu(tsk_index);
154 }
155
156 do_sleep = 0;
157
158 expire_time = jiffies + HZ * (100 - idle_pct) / 100;
159
160 while (!need_resched()) {
161 if (tsc_detected_unstable && !tsc_marked_unstable) {
162 /* TSC could halt in idle, so notify users */
163 mark_tsc_unstable("TSC halts in idle");
164 tsc_marked_unstable = 1;
165 }
166 local_irq_disable();
167
> 168 perf_lopwr_cb(true);
169
170 tick_broadcast_enable();
171 tick_broadcast_enter();
172 stop_critical_timings();
173
174 mwait_idle_with_hints(power_saving_mwait_eax, 1);
175
176 start_critical_timings();
177 tick_broadcast_exit();
178
179 perf_lopwr_cb(false);
180
181 local_irq_enable();
182
183 if (time_before(expire_time, jiffies)) {
184 do_sleep = 1;
185 break;
186 }
187 }
188
189 /*
190 * current sched_rt has threshold for rt task running time.
191 * When a rt task uses 95% CPU time, the rt thread will be
192 * scheduled out for 5% CPU time to not starve other tasks. But
193 * the mechanism only works when all CPUs have RT task running,
194 * as if one CPU hasn't RT task, RT task from other CPUs will
195 * borrow CPU time from this CPU and cause RT task use > 95%
196 * CPU time. To make 'avoid starvation' work, takes a nap here.
197 */
198 if (unlikely(do_sleep))
199 schedule_timeout_killable(HZ * idle_pct / 100);
200
201 /* If an external event has set the need_resched flag, then
202 * we need to deal with it, or this loop will continue to
203 * spin without calling __mwait().
204 */
205 if (unlikely(need_resched()))
206 schedule();
207 }
208
209 exit_round_robin(tsk_index);
210 return 0;
211 }
212
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
Re: [PATCH 2/2] Remove bdi_congested() and wb_congested() and related functions
by kernel test robot
Hi NeilBrown,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on hnaz-mm/master]
[also build test WARNING on axboe-block/for-next konis-nilfs2/upstream xfs-linux/for-next linus/master v5.16-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/NeilBrown/Remove-some-congested-...
base: https://github.com/hnaz/linux-mm master
config: arc-randconfig-r015-20211213 (https://download.01.org/0day-ci/archive/20211213/202112131323.fj31o6EV-lk...)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/41802b6debbde3d5553a8067ba2deb203...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review NeilBrown/Remove-some-congested-tests/20211213-121653
git checkout 41802b6debbde3d5553a8067ba2deb2035e6da6e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash fs/ext2/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
fs/ext2/ialloc.c: In function 'ext2_preread_inode':
>> fs/ext2/ialloc.c:173:34: warning: variable 'bdi' set but not used [-Wunused-but-set-variable]
173 | struct backing_dev_info *bdi;
| ^~~
vim +/bdi +173 fs/ext2/ialloc.c
^1da177e4c3f41 Linus Torvalds 2005-04-16 154
^1da177e4c3f41 Linus Torvalds 2005-04-16 155 /*
^1da177e4c3f41 Linus Torvalds 2005-04-16 156 * We perform asynchronous prereading of the new inode's inode block when
^1da177e4c3f41 Linus Torvalds 2005-04-16 157 * we create the inode, in the expectation that the inode will be written
^1da177e4c3f41 Linus Torvalds 2005-04-16 158 * back soon. There are two reasons:
^1da177e4c3f41 Linus Torvalds 2005-04-16 159 *
^1da177e4c3f41 Linus Torvalds 2005-04-16 160 * - When creating a large number of files, the async prereads will be
^1da177e4c3f41 Linus Torvalds 2005-04-16 161 * nicely merged into large reads
^1da177e4c3f41 Linus Torvalds 2005-04-16 162 * - When writing out a large number of inodes, we don't need to keep on
^1da177e4c3f41 Linus Torvalds 2005-04-16 163 * stalling the writes while we read the inode block.
^1da177e4c3f41 Linus Torvalds 2005-04-16 164 *
^1da177e4c3f41 Linus Torvalds 2005-04-16 165 * FIXME: ext2_get_group_desc() needs to be simplified.
^1da177e4c3f41 Linus Torvalds 2005-04-16 166 */
^1da177e4c3f41 Linus Torvalds 2005-04-16 167 static void ext2_preread_inode(struct inode *inode)
^1da177e4c3f41 Linus Torvalds 2005-04-16 168 {
^1da177e4c3f41 Linus Torvalds 2005-04-16 169 unsigned long block_group;
^1da177e4c3f41 Linus Torvalds 2005-04-16 170 unsigned long offset;
^1da177e4c3f41 Linus Torvalds 2005-04-16 171 unsigned long block;
^1da177e4c3f41 Linus Torvalds 2005-04-16 172 struct ext2_group_desc * gdp;
^1da177e4c3f41 Linus Torvalds 2005-04-16 @173 struct backing_dev_info *bdi;
^1da177e4c3f41 Linus Torvalds 2005-04-16 174
de1414a654e66b Christoph Hellwig 2015-01-14 175 bdi = inode_to_bdi(inode);
^1da177e4c3f41 Linus Torvalds 2005-04-16 176
^1da177e4c3f41 Linus Torvalds 2005-04-16 177 block_group = (inode->i_ino - 1) / EXT2_INODES_PER_GROUP(inode->i_sb);
ef2fb67989d30f Eric Sandeen 2007-10-16 178 gdp = ext2_get_group_desc(inode->i_sb, block_group, NULL);
^1da177e4c3f41 Linus Torvalds 2005-04-16 179 if (gdp == NULL)
^1da177e4c3f41 Linus Torvalds 2005-04-16 180 return;
^1da177e4c3f41 Linus Torvalds 2005-04-16 181
^1da177e4c3f41 Linus Torvalds 2005-04-16 182 /*
^1da177e4c3f41 Linus Torvalds 2005-04-16 183 * Figure out the offset within the block group inode table
^1da177e4c3f41 Linus Torvalds 2005-04-16 184 */
^1da177e4c3f41 Linus Torvalds 2005-04-16 185 offset = ((inode->i_ino - 1) % EXT2_INODES_PER_GROUP(inode->i_sb)) *
^1da177e4c3f41 Linus Torvalds 2005-04-16 186 EXT2_INODE_SIZE(inode->i_sb);
^1da177e4c3f41 Linus Torvalds 2005-04-16 187 block = le32_to_cpu(gdp->bg_inode_table) +
^1da177e4c3f41 Linus Torvalds 2005-04-16 188 (offset >> EXT2_BLOCK_SIZE_BITS(inode->i_sb));
^1da177e4c3f41 Linus Torvalds 2005-04-16 189 sb_breadahead(inode->i_sb, block);
^1da177e4c3f41 Linus Torvalds 2005-04-16 190 }
^1da177e4c3f41 Linus Torvalds 2005-04-16 191
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week
[arm:zii 147/186] drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1531:49: error: incompatible pointer types passing 'struct phylink_config *' to parameter of type 'struct phylink_pcs *'
by kernel test robot
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git zii
head: bc8489278c9545054f74b2226d3e2c09ec4e05fe
commit: 7123048813642c4842fcf8e6f4ce6315926cc164 [147/186] net: axienet: convert to phylink_pcs
config: riscv-randconfig-c006-20211212 (https://download.01.org/0day-ci/archive/20211213/202112131233.tkpcN3nU-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
git remote add arm git://git.armlinux.org.uk/~rmk/linux-arm.git
git fetch --no-tags arm zii
git checkout 7123048813642c4842fcf8e6f4ce6315926cc164
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/net/ethernet/xilinx/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1523:33: error: use of undeclared identifier 'lp'
phylink_mii_c22_pcs_an_restart(lp->pcs_phy);
^
>> drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1531:49: error: incompatible pointer types passing 'struct phylink_config *' to parameter of type 'struct phylink_pcs *' [-Werror,-Wincompatible-pointer-types]
struct net_device *ndev = pcs_to_axienet_local(pcs)->ndev;
^~~
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1506:71: note: passing argument to parameter 'pcs' here
static struct axienet_local *pcs_to_axienet_local(struct phylink_pcs *pcs)
^
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1532:53: error: incompatible pointer types passing 'struct phylink_config *' to parameter of type 'struct phylink_pcs *' [-Werror,-Wincompatible-pointer-types]
struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy;
^~~
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1506:71: note: passing argument to parameter 'pcs' here
static struct axienet_local *pcs_to_axienet_local(struct phylink_pcs *pcs)
^
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1537:8: error: use of undeclared identifier 'iface'
iface == PHY_INTERFACE_MODE_SGMII ?
^
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1554:16: error: incompatible function pointer types initializing 'int (*)(struct phylink_pcs *, unsigned int, phy_interface_t, const unsigned long *, bool)' (aka 'int (*)(struct phylink_pcs *, unsigned int, phy_interface_t, const unsigned long *, _Bool)') with an expression of type 'int (struct phylink_config *, unsigned int, phy_interface_t, const unsigned long *, bool)' (aka 'int (struct phylink_config *, unsigned int, phy_interface_t, const unsigned long *, _Bool)') [-Werror,-Wincompatible-function-pointer-types]
.pcs_config = axienet_pcs_config,
^~~~~~~~~~~~~~~~~~
5 errors generated.
vim +1531 drivers/net/ethernet/xilinx/xilinx_axienet_main.c
1525
1526 static int axienet_pcs_config(struct phylink_config *pcs, unsigned int mode,
1527 phy_interface_t interface,
1528 const unsigned long *advertising,
1529 bool permit_pause_to_mac)
1530 {
> 1531 struct net_device *ndev = pcs_to_axienet_local(pcs)->ndev;
1532 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy;
1533 int ret;
1534
1535 ret = mdiobus_write(pcs_phy->bus, pcs_phy->addr,
1536 XLNX_MII_STD_SELECT_REG,
1537 iface == PHY_INTERFACE_MODE_SGMII ?
1538 XLNX_MII_STD_SELECT_SGMII : 0);
1539 if (ret < 0) {
1540 netdev_warn(ndev, "Failed to switch PHY interface: %d\n",
1541 ret);
1542 return ret;
1543 }
1544
1545 ret = phylink_mii_c22_pcs_config(pcs_phy, mode, interface, advertising);
1546 if (ret < 0)
1547 netdev_warn(ndev, "Failed to configure PCS: %d\n", ret);
1548
1549 return ret;
1550 }
1551
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
9 months, 1 week