Robar Cuentas Por ID
by gerdajocelynai＠gmail.com
Robar Cuentas Por id is a program which allows you to hack into your accounts using ID technology. It works by stealing your password and email address. It doesn't require any user interaction. It can be installed on any device and is free to download from any source. To get started, simply go to the official website and download the APK file. Confirm its installation and wait for a minute or two. Once installed, the program will display "Open".[url=https://modpree.com/robar-cuentas-por-id/]https://modpree.com/robar-cuentas-por-id/[/url]
Robar Cuentas Por ID is a free app for Android devices. Just download the APK file from the official website or a third-party store and install it on your device. You can then get the documents you need to hack the account. This application is designed to be easy to use and is suitable for most Android devices. It is very safe to use, but you need to be careful.
You can download the app by clicking on the button below. Once you have downloaded the application, you can follow the instructions to install it. You don't need to worry about its safety as it is updated regularly. If you're worried about security, you can always check the APK file from the play store or es file explorer. However, if you're unsure, you can always go to the official website of Robar Cuentas Por id to make sure you're not downloading a malicious application.
If you'd like to download the Robar Cuentas por id APK file for your Android device, just visit the website listed above. Then, simply tap on the APK file and wait for it to download. Once the installation is complete, you'll see the "Open" message in the app. If you're unsure about the process, check with your device's settings or browser.
After you've downloaded Robar Cuentas por id, you can open it from any location in the Internet. You'll need to allow the app to install itself. Once you have allowed it to install, you will see a confirmation window in your browser. You'll then need to sign into your account and access your private information. You can use the app to download Facebook and other social networks and get more information about your friends.
The Robar Cuentas por id application will be available for download in the Downloads section of your device. Then, you'll need to install the application. The APK file will be stored on the memory card or system memory of your device. You should avoid opening a file that is not signed. After installing Robar Cuentas Por id, the application will be ready to be used.
8 months
Robar Cuentas Por ID
by gerdajocelynai＠gmail.com
Robar Cuentas Por id is a program which allows you to hack into your accounts using ID technology. It works by stealing your password and email address. It doesn't require any user interaction. It can be installed on any device and is free to download from any source. To get started, simply go to the official website and download the APK file. Confirm its installation and wait for a minute or two. Once installed, the program will display "Open".<a href="https://modpree.com/robar-cuentas-por-id/">https://modpree.com/robar-cuentas-por-id/</a>
Robar Cuentas Por ID is a free app for Android devices. Just download the APK file from the official website or a third-party store and install it on your device. You can then get the documents you need to hack the account. This application is designed to be easy to use and is suitable for most Android devices. It is very safe to use, but you need to be careful.
You can download the app by clicking on the button below. Once you have downloaded the application, you can follow the instructions to install it. You don't need to worry about its safety as it is updated regularly. If you're worried about security, you can always check the APK file from the play store or es file explorer. However, if you're unsure, you can always go to the official website of Robar Cuentas Por id to make sure you're not downloading a malicious application.
If you'd like to download the Robar Cuentas por id APK file for your Android device, just visit the website listed above. Then, simply tap on the APK file and wait for it to download. Once the installation is complete, you'll see the "Open" message in the app. If you're unsure about the process, check with your device's settings or browser.
After you've downloaded Robar Cuentas por id, you can open it from any location in the Internet. You'll need to allow the app to install itself. Once you have allowed it to install, you will see a confirmation window in your browser. You'll then need to sign into your account and access your private information. You can use the app to download Facebook and other social networks and get more information about your friends.
The Robar Cuentas por id application will be available for download in the Downloads section of your device. Then, you'll need to install the application. The APK file will be stored on the memory card or system memory of your device. You should avoid opening a file that is not signed. After installing Robar Cuentas Por id, the application will be ready to be used.
8 months
Robar Cuentas Por ID
by gerdajocelynai＠gmail.com
Robar Cuentas Por id is a program which allows you to hack into your accounts using ID technology. It works by stealing your password and email address. It doesn't require any user interaction. It can be installed on any device and is free to download from any source. To get started, simply go to the official website and download the APK file. Confirm its installation and wait for a minute or two. Once installed, the program will display "Open".https://modpree.com/robar-cuentas-por-id/
Robar Cuentas Por ID is a free app for Android devices. Just download the APK file from the official website or a third-party store and install it on your device. You can then get the documents you need to hack the account. This application is designed to be easy to use and is suitable for most Android devices. It is very safe to use, but you need to be careful.
You can download the app by clicking on the button below. Once you have downloaded the application, you can follow the instructions to install it. You don't need to worry about its safety as it is updated regularly. If you're worried about security, you can always check the APK file from the play store or es file explorer. However, if you're unsure, you can always go to the official website of Robar Cuentas Por id to make sure you're not downloading a malicious application.
If you'd like to download the Robar Cuentas por id APK file for your Android device, just visit the website listed above. Then, simply tap on the APK file and wait for it to download. Once the installation is complete, you'll see the "Open" message in the app. If you're unsure about the process, check with your device's settings or browser.
After you've downloaded Robar Cuentas por id, you can open it from any location in the Internet. You'll need to allow the app to install itself. Once you have allowed it to install, you will see a confirmation window in your browser. You'll then need to sign into your account and access your private information. You can use the app to download Facebook and other social networks and get more information about your friends.
The Robar Cuentas por id application will be available for download in the Downloads section of your device. Then, you'll need to install the application. The APK file will be stored on the memory card or system memory of your device. You should avoid opening a file that is not signed. After installing Robar Cuentas Por id, the application will be ready to be used.
8 months
[rmk-arm:zii 76/167] drivers/net/dsa/qca8k.c:1479:1: warning: conflicting types for 'qca8k_mac_config_setup_internal_delay'; have 'void(struct qca8k_priv *, int, u32)' {aka 'void(struct qca8k_priv *, int, unsigned int)'}
by kernel test robot
tree: git://git.armlinux.org.uk/~rmk/linux-arm zii
head: 2c17c82cf0078ead3d8a315b2b103f9e5a5cdb1d
commit: c1b605b3b2edac51ad6b687c68f087fe166790ce [76/167] net: dsa: qca8k: convert to use phylink_pcs
config: arc-randconfig-r043-20220118 (https://download.01.org/0day-ci/archive/20220118/202201181202.Fx7O6xnh-lk...)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add rmk-arm git://git.armlinux.org.uk/~rmk/linux-arm
git fetch --no-tags rmk-arm zii
git checkout c1b605b3b2edac51ad6b687c68f087fe166790ce
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash drivers/net/dsa/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
drivers/net/dsa/qca8k.c: In function 'qca8k_pcs_config':
drivers/net/dsa/qca8k.c:1185:17: error: implicit declaration of function 'qca8k_mac_config_setup_internal_delay' [-Werror=implicit-function-declaration]
1185 | qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/qca8k.c: At top level:
>> drivers/net/dsa/qca8k.c:1479:1: warning: conflicting types for 'qca8k_mac_config_setup_internal_delay'; have 'void(struct qca8k_priv *, int, u32)' {aka 'void(struct qca8k_priv *, int, unsigned int)'}
1479 | qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/qca8k.c:1479:1: error: static declaration of 'qca8k_mac_config_setup_internal_delay' follows non-static declaration
drivers/net/dsa/qca8k.c:1185:17: note: previous implicit declaration of 'qca8k_mac_config_setup_internal_delay' with type 'void(struct qca8k_priv *, int, u32)' {aka 'void(struct qca8k_priv *, int, unsigned int)'}
1185 | qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +1479 drivers/net/dsa/qca8k.c
c1b605b3b2edac Russell King (Oracle 2021-11-23 1477)
cef08115846e58 Ansuel Smith 2021-10-14 1478 static void
cef08115846e58 Ansuel Smith 2021-10-14 @1479 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
cef08115846e58 Ansuel Smith 2021-10-14 1480 u32 reg)
cef08115846e58 Ansuel Smith 2021-10-14 1481 {
cef08115846e58 Ansuel Smith 2021-10-14 1482 u32 delay, val = 0;
cef08115846e58 Ansuel Smith 2021-10-14 1483 int ret;
cef08115846e58 Ansuel Smith 2021-10-14 1484
cef08115846e58 Ansuel Smith 2021-10-14 1485 /* Delay can be declared in 3 different way.
cef08115846e58 Ansuel Smith 2021-10-14 1486 * Mode to rgmii and internal-delay standard binding defined
cef08115846e58 Ansuel Smith 2021-10-14 1487 * rgmii-id or rgmii-tx/rx phy mode set.
cef08115846e58 Ansuel Smith 2021-10-14 1488 * The parse logic set a delay different than 0 only when one
cef08115846e58 Ansuel Smith 2021-10-14 1489 * of the 3 different way is used. In all other case delay is
cef08115846e58 Ansuel Smith 2021-10-14 1490 * not enabled. With ID or TX/RXID delay is enabled and set
cef08115846e58 Ansuel Smith 2021-10-14 1491 * to the default and recommended value.
cef08115846e58 Ansuel Smith 2021-10-14 1492 */
fd0bb28c547f7c Ansuel Smith 2021-10-14 1493 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
fd0bb28c547f7c Ansuel Smith 2021-10-14 1494 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
cef08115846e58 Ansuel Smith 2021-10-14 1495
cef08115846e58 Ansuel Smith 2021-10-14 1496 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
cef08115846e58 Ansuel Smith 2021-10-14 1497 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
cef08115846e58 Ansuel Smith 2021-10-14 1498 }
cef08115846e58 Ansuel Smith 2021-10-14 1499
fd0bb28c547f7c Ansuel Smith 2021-10-14 1500 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
fd0bb28c547f7c Ansuel Smith 2021-10-14 1501 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
cef08115846e58 Ansuel Smith 2021-10-14 1502
cef08115846e58 Ansuel Smith 2021-10-14 1503 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
cef08115846e58 Ansuel Smith 2021-10-14 1504 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
cef08115846e58 Ansuel Smith 2021-10-14 1505 }
cef08115846e58 Ansuel Smith 2021-10-14 1506
cef08115846e58 Ansuel Smith 2021-10-14 1507 /* Set RGMII delay based on the selected values */
cef08115846e58 Ansuel Smith 2021-10-14 1508 ret = qca8k_rmw(priv, reg,
cef08115846e58 Ansuel Smith 2021-10-14 1509 QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
cef08115846e58 Ansuel Smith 2021-10-14 1510 QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
cef08115846e58 Ansuel Smith 2021-10-14 1511 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
cef08115846e58 Ansuel Smith 2021-10-14 1512 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
cef08115846e58 Ansuel Smith 2021-10-14 1513 val);
cef08115846e58 Ansuel Smith 2021-10-14 1514 if (ret)
cef08115846e58 Ansuel Smith 2021-10-14 1515 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
cef08115846e58 Ansuel Smith 2021-10-14 1516 cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
cef08115846e58 Ansuel Smith 2021-10-14 1517 }
cef08115846e58 Ansuel Smith 2021-10-14 1518
:::::: The code at line 1479 was first introduced by commit
:::::: cef08115846e581f80ff99abf7bf218da1840616 net: dsa: qca8k: set internal delay also for sgmii
:::::: TO: Ansuel Smith <ansuelsmth(a)gmail.com>
:::::: CC: David S. Miller <davem(a)davemloft.net>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months
arch/arm64/kernel/hibernate.c:202:44: sparse: sparse: cast from restricted gfp_t
by kernel test robot
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 0c947b893d69231a9add855939da7c66237ab44f
commit: 50f53fb721817a6efa541cca24f1b7caa84801c1 arm64: trans_pgd: make trans_pgd_map_page generic
date: 12 months ago
config: arm64-randconfig-s031-20220117 (https://download.01.org/0day-ci/archive/20220118/202201181248.rDauB3ns-lk...)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit...
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 50f53fb721817a6efa541cca24f1b7caa84801c1
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/kernel/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
sparse warnings: (new ones prefixed by >>)
arch/arm64/kernel/hibernate.c:181:39: sparse: sparse: cast to restricted gfp_t
>> arch/arm64/kernel/hibernate.c:202:44: sparse: sparse: cast from restricted gfp_t
vim +202 arch/arm64/kernel/hibernate.c
183
184 /*
185 * Copies length bytes, starting at src_start into an new page,
186 * perform cache maintenance, then maps it at the specified address low
187 * address as executable.
188 *
189 * This is used by hibernate to copy the code it needs to execute when
190 * overwriting the kernel text. This function generates a new set of page
191 * tables, which it loads into ttbr0.
192 *
193 * Length is provided as we probably only want 4K of data, even on a 64K
194 * page system.
195 */
196 static int create_safe_exec_page(void *src_start, size_t length,
197 unsigned long dst_addr,
198 phys_addr_t *phys_dst_addr)
199 {
200 struct trans_pgd_info trans_info = {
201 .trans_alloc_page = hibernate_page_alloc,
> 202 .trans_alloc_arg = (void *)GFP_ATOMIC,
203 };
204
205 void *page = (void *)get_safe_page(GFP_ATOMIC);
206 pgd_t *trans_pgd;
207 int rc;
208
209 if (!page)
210 return -ENOMEM;
211
212 memcpy(page, src_start, length);
213 __flush_icache_range((unsigned long)page, (unsigned long)page + length);
214
215 trans_pgd = (void *)get_safe_page(GFP_ATOMIC);
216 if (!trans_pgd)
217 return -ENOMEM;
218
219 rc = trans_pgd_map_page(&trans_info, trans_pgd, page, dst_addr,
220 PAGE_KERNEL_EXEC);
221 if (rc)
222 return rc;
223
224 /*
225 * Load our new page tables. A strict BBM approach requires that we
226 * ensure that TLBs are free of any entries that may overlap with the
227 * global mappings we are about to install.
228 *
229 * For a real hibernate/resume cycle TTBR0 currently points to a zero
230 * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI
231 * runtime services), while for a userspace-driven test_resume cycle it
232 * points to userspace page tables (and we must point it at a zero page
233 * ourselves). Elsewhere we only (un)install the idmap with preemption
234 * disabled, so T0SZ should be as required regardless.
235 */
236 cpu_set_reserved_ttbr0();
237 local_flush_tlb_all();
238 write_sysreg(phys_to_ttbr(virt_to_phys(trans_pgd)), ttbr0_el1);
239 isb();
240
241 *phys_dst_addr = virt_to_phys(page);
242
243 return 0;
244 }
245
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:2106:13: warning: stack frame size (2136) exceeds limit (2048) in 'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation'
by kernel test robot
Hi Alex,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 0c947b893d69231a9add855939da7c66237ab44f
commit: 8fe44c080a53ac0ccbe88053a2e40f9acca33091 drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN
date: 7 months ago
config: x86_64-randconfig-r004-20220117 (https://download.01.org/0day-ci/archive/20220118/202201181113.zMONHfro-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project c63a3175c2947e8c1a2d3bbe16a8586600705c54)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit...
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 8fe44c080a53ac0ccbe88053a2e40f9acca33091
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:2106:13: warning: stack frame size (2136) exceeds limit (2048) in 'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation' [-Wframe-larger-than]
static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib)
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3957:6: warning: stack frame size (3384) exceeds limit (2048) in 'dml31_ModeSupportAndSystemConfigurationFull' [-Wframe-larger-than]
void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
^
2 warnings generated.
vim +/DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation +2106 drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2105
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 @2106 static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2107 {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2108 struct vba_vars_st *v = &mode_lib->vba;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2109 unsigned int j, k;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2110 double HostVMInefficiencyFactor = 1.0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2111 bool NoChromaPlanes = true;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2112 int ReorderBytes;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2113 double VMDataOnlyReturnBW;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2114 double MaxTotalRDBandwidth = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2115 int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2116
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2117 v->WritebackDISPCLK = 0.0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2118 v->DISPCLKWithRamping = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2119 v->DISPCLKWithoutRamping = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2120 v->GlobalDPPCLK = 0.0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2121 /* DAL custom code: need to update ReturnBW in case min dcfclk is overriden */
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2122 {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2123 double IdealFabricAndSDPPortBandwidthPerState = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2124 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2125 v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2126 double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2127 if (v->HostVMEnable != true) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2128 v->ReturnBW = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2129 IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2130 IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2131 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2132 v->ReturnBW = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2133 IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2134 IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2135 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2136 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2137 /* End DAL custom code */
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2138
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2139 // DISPCLK and DPPCLK Calculation
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2140 //
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2141 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2142 if (v->WritebackEnable[k]) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2143 v->WritebackDISPCLK = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2144 v->WritebackDISPCLK,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2145 dml31_CalculateWriteBackDISPCLK(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2146 v->WritebackPixelFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2147 v->PixelClock[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2148 v->WritebackHRatio[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2149 v->WritebackVRatio[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2150 v->WritebackHTaps[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2151 v->WritebackVTaps[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2152 v->WritebackSourceWidth[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2153 v->WritebackDestinationWidth[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2154 v->HTotal[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2155 v->WritebackLineBufferSize));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2156 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2157 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2158
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2159 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2160 if (v->HRatio[k] > 1) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2161 v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2162 v->MaxDCHUBToPSCLThroughput,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2163 v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2164 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2165 v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2166 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2167
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2168 v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2169 * dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2170 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2171 dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2172
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2173 if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2174 v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2175 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2176
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2177 if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2178 && v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2179 v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2180 v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2181 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2182 if (v->HRatioChroma[k] > 1) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2183 v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2184 v->MaxDCHUBToPSCLThroughput,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2185 v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2186 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2187 v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2188 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2189 v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2190 * dml_max3(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2191 v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2192 v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2193 1.0);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2194
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2195 if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2196 v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2197 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2198
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2199 v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2200 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2201 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2202
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2203 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2204 if (v->BlendingAndTiming[k] != k)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2205 continue;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2206 if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2207 v->DISPCLKWithRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2208 v->DISPCLKWithRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2209 v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2210 * (1 + v->DISPCLKRampingMargin / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2211 v->DISPCLKWithoutRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2212 v->DISPCLKWithoutRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2213 v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2214 } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2215 v->DISPCLKWithRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2216 v->DISPCLKWithRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2217 v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2218 * (1 + v->DISPCLKRampingMargin / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2219 v->DISPCLKWithoutRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2220 v->DISPCLKWithoutRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2221 v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2222 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2223 v->DISPCLKWithRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2224 v->DISPCLKWithRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2225 v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2226 v->DISPCLKWithoutRamping = dml_max(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2227 v->DISPCLKWithoutRamping,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2228 v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2229 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2230 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2231
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2232 v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2233 v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2234
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2235 ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2236 v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2237 v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2238 v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2239 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2240 v->DISPCLKDPPCLKVCOSpeed);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2241 if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2242 v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2243 } else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2244 v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2245 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2246 v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2247 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2248 v->DISPCLK = v->DISPCLK_calculated;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2249 DTRACE(" dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2250
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2251 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2252 v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2253 v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2254 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2255 v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2256 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2257 v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2258 DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2259 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2260
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2261 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2262 v->DPPCLK[k] = v->DPPCLK_calculated[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2263 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2264
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2265 // Urgent and B P-State/DRAM Clock Change Watermark
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2266 DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2267 DTRACE(" return_bus_bw = %f", v->ReturnBW);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2268
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2269 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2270 CalculateBytePerPixelAnd256BBlockSizes(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2271 v->SourcePixelFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2272 v->SurfaceTiling[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2273 &v->BytePerPixelY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2274 &v->BytePerPixelC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2275 &v->BytePerPixelDETY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2276 &v->BytePerPixelDETC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2277 &v->BlockHeight256BytesY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2278 &v->BlockHeight256BytesC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2279 &v->BlockWidth256BytesY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2280 &v->BlockWidth256BytesC[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2281 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2282
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2283 CalculateSwathWidth(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2284 false,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2285 v->NumberOfActivePlanes,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2286 v->SourcePixelFormat,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2287 v->SourceScan,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2288 v->ViewportWidth,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2289 v->ViewportHeight,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2290 v->SurfaceWidthY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2291 v->SurfaceWidthC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2292 v->SurfaceHeightY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2293 v->SurfaceHeightC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2294 v->ODMCombineEnabled,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2295 v->BytePerPixelY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2296 v->BytePerPixelC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2297 v->BlockHeight256BytesY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2298 v->BlockHeight256BytesC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2299 v->BlockWidth256BytesY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2300 v->BlockWidth256BytesC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2301 v->BlendingAndTiming,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2302 v->HActive,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2303 v->HRatio,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2304 v->DPPPerPlane,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2305 v->SwathWidthSingleDPPY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2306 v->SwathWidthSingleDPPC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2307 v->SwathWidthY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2308 v->SwathWidthC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2309 v->dummyinteger3,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2310 v->dummyinteger4,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2311 v->swath_width_luma_ub,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2312 v->swath_width_chroma_ub);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2313
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2314 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2315 v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2316 * v->VRatio[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2317 v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2318 * v->VRatioChroma[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2319 DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2320 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2321
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2322 // DCFCLK Deep Sleep
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2323 CalculateDCFCLKDeepSleep(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2324 mode_lib,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2325 v->NumberOfActivePlanes,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2326 v->BytePerPixelY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2327 v->BytePerPixelC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2328 v->VRatio,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2329 v->VRatioChroma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2330 v->SwathWidthY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2331 v->SwathWidthC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2332 v->DPPPerPlane,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2333 v->HRatio,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2334 v->HRatioChroma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2335 v->PixelClock,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2336 v->PSCL_THROUGHPUT_LUMA,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2337 v->PSCL_THROUGHPUT_CHROMA,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2338 v->DPPCLK,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2339 v->ReadBandwidthPlaneLuma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2340 v->ReadBandwidthPlaneChroma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2341 v->ReturnBusWidth,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2342 &v->DCFCLKDeepSleep);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2343
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2344 // DSCCLK
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2345 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2346 if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2347 v->DSCCLK_calculated[k] = 0.0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2348 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2349 if (v->OutputFormat[k] == dm_420)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2350 v->DSCFormatFactor = 2;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2351 else if (v->OutputFormat[k] == dm_444)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2352 v->DSCFormatFactor = 1;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2353 else if (v->OutputFormat[k] == dm_n422)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2354 v->DSCFormatFactor = 2;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2355 else
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2356 v->DSCFormatFactor = 1;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2357 if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2358 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2359 / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2360 else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2361 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2362 / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2363 else
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2364 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2365 / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2366 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2367 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2368
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2369 // DSC Delay
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2370 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2371 double BPP = v->OutputBpp[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2372
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2373 if (v->DSCEnabled[k] && BPP != 0) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2374 if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2375 v->DSCDelay[k] = dscceComputeDelay(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2376 v->DSCInputBitPerComponent[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2377 BPP,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2378 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2379 v->NumberOfDSCSlices[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2380 v->OutputFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2381 v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2382 } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2383 v->DSCDelay[k] = 2
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2384 * (dscceComputeDelay(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2385 v->DSCInputBitPerComponent[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2386 BPP,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2387 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2388 v->NumberOfDSCSlices[k] / 2.0,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2389 v->OutputFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2390 v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2391 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2392 v->DSCDelay[k] = 4
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2393 * (dscceComputeDelay(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2394 v->DSCInputBitPerComponent[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2395 BPP,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2396 dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2397 v->NumberOfDSCSlices[k] / 4.0,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2398 v->OutputFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2399 v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2400 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2401 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2402 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2403 v->DSCDelay[k] = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2404 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2405 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2406
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2407 for (k = 0; k < v->NumberOfActivePlanes; ++k)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2408 for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2409 if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2410 v->DSCDelay[k] = v->DSCDelay[j];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2411
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2412 // Prefetch
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2413 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2414 unsigned int PDEAndMetaPTEBytesFrameY;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2415 unsigned int PixelPTEBytesPerRowY;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2416 unsigned int MetaRowByteY;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2417 unsigned int MetaRowByteC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2418 unsigned int PDEAndMetaPTEBytesFrameC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2419 unsigned int PixelPTEBytesPerRowC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2420 bool PTEBufferSizeNotExceededY;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2421 bool PTEBufferSizeNotExceededC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2422
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2423 if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2424 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2425 if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2426 v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2427 v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2428 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2429 v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2430 v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2431 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2432
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2433 PDEAndMetaPTEBytesFrameC = CalculateVMAndRowBytes(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2434 mode_lib,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2435 v->DCCEnable[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2436 v->BlockHeight256BytesC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2437 v->BlockWidth256BytesC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2438 v->SourcePixelFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2439 v->SurfaceTiling[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2440 v->BytePerPixelC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2441 v->SourceScan[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2442 v->SwathWidthC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2443 v->ViewportHeightChroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2444 v->GPUVMEnable,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2445 v->HostVMEnable,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2446 v->HostVMMaxNonCachedPageTableLevels,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2447 v->GPUVMMinPageSize,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2448 v->HostVMMinPageSize,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2449 v->PTEBufferSizeInRequestsForChroma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2450 v->PitchC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2451 v->DCCMetaPitchC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2452 &v->MacroTileWidthC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2453 &MetaRowByteC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2454 &PixelPTEBytesPerRowC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2455 &PTEBufferSizeNotExceededC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2456 &v->dpte_row_width_chroma_ub[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2457 &v->dpte_row_height_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2458 &v->meta_req_width_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2459 &v->meta_req_height_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2460 &v->meta_row_width_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2461 &v->meta_row_height_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2462 &v->dummyinteger1,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2463 &v->dummyinteger2,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2464 &v->PixelPTEReqWidthC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2465 &v->PixelPTEReqHeightC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2466 &v->PTERequestSizeC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2467 &v->dpde0_bytes_per_frame_ub_c[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2468 &v->meta_pte_bytes_per_frame_ub_c[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2469
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2470 v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2471 mode_lib,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2472 v->VRatioChroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2473 v->VTAPsChroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2474 v->Interlace[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2475 v->ProgressiveToInterlaceUnitInOPP,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2476 v->SwathHeightC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2477 v->ViewportYStartC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2478 &v->VInitPreFillC[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2479 &v->MaxNumSwathC[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2480 } else {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2481 v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2482 v->PTEBufferSizeInRequestsForChroma = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2483 PixelPTEBytesPerRowC = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2484 PDEAndMetaPTEBytesFrameC = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2485 MetaRowByteC = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2486 v->MaxNumSwathC[k] = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2487 v->PrefetchSourceLinesC[k] = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2488 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2489
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2490 PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2491 mode_lib,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2492 v->DCCEnable[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2493 v->BlockHeight256BytesY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2494 v->BlockWidth256BytesY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2495 v->SourcePixelFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2496 v->SurfaceTiling[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2497 v->BytePerPixelY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2498 v->SourceScan[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2499 v->SwathWidthY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2500 v->ViewportHeight[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2501 v->GPUVMEnable,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2502 v->HostVMEnable,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2503 v->HostVMMaxNonCachedPageTableLevels,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2504 v->GPUVMMinPageSize,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2505 v->HostVMMinPageSize,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2506 v->PTEBufferSizeInRequestsForLuma,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2507 v->PitchY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2508 v->DCCMetaPitchY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2509 &v->MacroTileWidthY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2510 &MetaRowByteY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2511 &PixelPTEBytesPerRowY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2512 &PTEBufferSizeNotExceededY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2513 &v->dpte_row_width_luma_ub[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2514 &v->dpte_row_height[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2515 &v->meta_req_width[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2516 &v->meta_req_height[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2517 &v->meta_row_width[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2518 &v->meta_row_height[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2519 &v->vm_group_bytes[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2520 &v->dpte_group_bytes[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2521 &v->PixelPTEReqWidthY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2522 &v->PixelPTEReqHeightY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2523 &v->PTERequestSizeY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2524 &v->dpde0_bytes_per_frame_ub_l[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2525 &v->meta_pte_bytes_per_frame_ub_l[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2526
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2527 v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2528 mode_lib,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2529 v->VRatio[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2530 v->vtaps[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2531 v->Interlace[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2532 v->ProgressiveToInterlaceUnitInOPP,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2533 v->SwathHeightY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2534 v->ViewportYStartY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2535 &v->VInitPreFillY[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2536 &v->MaxNumSwathY[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2537 v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2538 v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2539 v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2540
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2541 CalculateRowBandwidth(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2542 v->GPUVMEnable,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2543 v->SourcePixelFormat[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2544 v->VRatio[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2545 v->VRatioChroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2546 v->DCCEnable[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2547 v->HTotal[k] / v->PixelClock[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2548 MetaRowByteY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2549 MetaRowByteC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2550 v->meta_row_height[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2551 v->meta_row_height_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2552 PixelPTEBytesPerRowY,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2553 PixelPTEBytesPerRowC,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2554 v->dpte_row_height[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2555 v->dpte_row_height_chroma[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2556 &v->meta_row_bw[k],
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2557 &v->dpte_row_bw[k]);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2558 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2559
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2560 v->TotalDCCActiveDPP = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2561 v->TotalActiveDPP = 0;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2562 for (k = 0; k < v->NumberOfActivePlanes; ++k) {
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2563 v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2564 if (v->DCCEnable[k])
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2565 v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2566 if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2567 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2568 NoChromaPlanes = false;
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2569 }
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2570
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2571 ReorderBytes = v->NumberOfChannels
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2572 * dml_max3(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2573 v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2574 v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2575 v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2576
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2577 VMDataOnlyReturnBW = dml_min(
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2578 dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2579 * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2580 v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2581 * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
74458c081fcfb0 Nicholas Kazlauskas 2021-05-19 2582
:::::: The code at line 2106 was first introduced by commit
:::::: 74458c081fcfb0423877e630de2746daefdb16e4 drm/amd/display: Add DCN3.1 DML calculation support
:::::: TO: Nicholas Kazlauskas <nicholas.kazlauskas(a)amd.com>
:::::: CC: Alex Deucher <alexander.deucher(a)amd.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months
[chrome-os:chromeos-5.10 9991/9999] sound/soc/sof/mediatek/mt8195/mt8195.c:50:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 4 has type 'unsigned int'
by kernel test robot
tree: https://chromium.googlesource.com/chromiumos/third_party/kernel chromeos-5.10
head: d2945e83762685e27b20286924d8e59daa10233f
commit: 61b770b79cf297ed40010e74b8fc1b55ab1e2aaa [9991/9999] UPSTREAM: ASoC: SOF: mediatek: Add mt8195 hardware support
config: nios2-allyesconfig (https://download.01.org/0day-ci/archive/20220118/202201181032.4rx9gA6K-lk...)
compiler: nios2-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add chrome-os https://chromium.googlesource.com/chromiumos/third_party/kernel
git fetch --no-tags chrome-os chromeos-5.10
git checkout 61b770b79cf297ed40010e74b8fc1b55ab1e2aaa
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nios2 SHELL=/bin/bash sound/soc/sof/mediatek/mt8195/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:409,
from include/linux/kernel.h:16,
from include/linux/delay.h:22,
from sound/soc/sof/mediatek/mt8195/mt8195.c:12:
sound/soc/sof/mediatek/mt8195/mt8195.c: In function 'platform_parse_resource':
>> sound/soc/sof/mediatek/mt8195/mt8195.c:50:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 4 has type 'unsigned int' [-Wformat=]
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:129:29: note: in definition of macro '__dynamic_func_call'
129 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:161:9: note: in expansion of macro '_dynamic_func_call'
161 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:9: note: in expansion of macro 'dynamic_dev_dbg'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:30: note: in expansion of macro 'dev_fmt'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:50:9: note: in expansion of macro 'dev_dbg'
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:50:38: note: format string is defined here
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ~~~^
| |
| long long unsigned int
| %x
In file included from include/linux/printk.h:409,
from include/linux/kernel.h:16,
from include/linux/delay.h:22,
from sound/soc/sof/mediatek/mt8195/mt8195.c:12:
>> sound/soc/sof/mediatek/mt8195/mt8195.c:50:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 5 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=]
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:129:29: note: in definition of macro '__dynamic_func_call'
129 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:161:9: note: in expansion of macro '_dynamic_func_call'
161 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:9: note: in expansion of macro 'dynamic_dev_dbg'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:30: note: in expansion of macro 'dev_fmt'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:50:9: note: in expansion of macro 'dev_dbg'
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:50:51: note: format string is defined here
50 | dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
| ~~~^
| |
| long long unsigned int
| %x
In file included from include/linux/printk.h:409,
from include/linux/kernel.h:16,
from include/linux/delay.h:22,
from sound/soc/sof/mediatek/mt8195/mt8195.c:12:
sound/soc/sof/mediatek/mt8195/mt8195.c: In function 'adsp_memory_remap_init':
>> sound/soc/sof/mediatek/mt8195/mt8195.c:166:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 4 has type 'phys_addr_t' {aka 'unsigned int'} [-Wformat=]
166 | dev_dbg(dev, "adsp->pa_dram %llx, offset %#x\n", adsp->pa_dram, offset);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:129:29: note: in definition of macro '__dynamic_func_call'
129 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:161:9: note: in expansion of macro '_dynamic_func_call'
161 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:9: note: in expansion of macro 'dynamic_dev_dbg'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:30: note: in expansion of macro 'dev_fmt'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:166:9: note: in expansion of macro 'dev_dbg'
166 | dev_dbg(dev, "adsp->pa_dram %llx, offset %#x\n", adsp->pa_dram, offset);
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:166:40: note: format string is defined here
166 | dev_dbg(dev, "adsp->pa_dram %llx, offset %#x\n", adsp->pa_dram, offset);
| ~~~^
| |
| long long unsigned int
| %x
In file included from include/linux/printk.h:409,
from include/linux/kernel.h:16,
from include/linux/delay.h:22,
from sound/soc/sof/mediatek/mt8195/mt8195.c:12:
sound/soc/sof/mediatek/mt8195/mt8195.c: In function 'adsp_shared_base_ioremap':
sound/soc/sof/mediatek/mt8195/mt8195.c:195:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 5 has type 'phys_addr_t' {aka 'unsigned int'} [-Wformat=]
195 | dev_dbg(dev, "shared-dram vbase=%p, phy addr :%llx, size=%#x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:129:29: note: in definition of macro '__dynamic_func_call'
129 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:161:9: note: in expansion of macro '_dynamic_func_call'
161 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:9: note: in expansion of macro 'dynamic_dev_dbg'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:30: note: in expansion of macro 'dev_fmt'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:195:9: note: in expansion of macro 'dev_dbg'
195 | dev_dbg(dev, "shared-dram vbase=%p, phy addr :%llx, size=%#x\n",
| ^~~~~~~
sound/soc/sof/mediatek/mt8195/mt8195.c:195:58: note: format string is defined here
195 | dev_dbg(dev, "shared-dram vbase=%p, phy addr :%llx, size=%#x\n",
| ~~~^
| |
| long long unsigned int
| %x
vim +50 sound/soc/sof/mediatek/mt8195/mt8195.c
28
29 static int platform_parse_resource(struct platform_device *pdev, void *data)
30 {
31 struct resource *mmio;
32 struct resource res;
33 struct device_node *mem_region;
34 struct device *dev = &pdev->dev;
35 struct mtk_adsp_chip_info *adsp = data;
36 int ret;
37
38 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
39 if (!mem_region) {
40 dev_err(dev, "no dma memory-region phandle\n");
41 return -ENODEV;
42 }
43
44 ret = of_address_to_resource(mem_region, 0, &res);
45 if (ret) {
46 dev_err(dev, "of_address_to_resource dma failed\n");
47 return ret;
48 }
49
> 50 dev_dbg(dev, "DMA pbase=0x%llx, size=0x%llx\n",
51 (phys_addr_t)res.start, resource_size(&res));
52
53 ret = of_reserved_mem_device_init(dev);
54 if (ret) {
55 dev_err(dev, "of_reserved_mem_device_init failed\n");
56 return ret;
57 }
58
59 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
60 if (!mem_region) {
61 dev_err(dev, "no memory-region sysmem phandle\n");
62 return -ENODEV;
63 }
64
65 ret = of_address_to_resource(mem_region, 0, &res);
66 if (ret) {
67 dev_err(dev, "of_address_to_resource sysmem failed\n");
68 return ret;
69 }
70
71 adsp->pa_dram = (phys_addr_t)res.start;
72 adsp->dramsize = resource_size(&res);
73 if (adsp->pa_dram & DRAM_REMAP_MASK) {
74 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
75 (u32)adsp->pa_dram);
76 return -EINVAL;
77 }
78
79 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
80 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
81 adsp->dramsize);
82 return -EINVAL;
83 }
84
85 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
86 &adsp->pa_dram, adsp->dramsize);
87
88 /* Parse CFG base */
89 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
90 if (!mmio) {
91 dev_err(dev, "no ADSP-CFG register resource\n");
92 return -ENXIO;
93 }
94 /* remap for DSP register accessing */
95 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
96 if (IS_ERR(adsp->va_cfgreg))
97 return PTR_ERR(adsp->va_cfgreg);
98
99 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
100 adsp->cfgregsize = resource_size(mmio);
101
102 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
103 adsp->va_cfgreg, adsp->cfgregsize);
104
105 /* Parse SRAM */
106 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
107 if (!mmio) {
108 dev_err(dev, "no SRAM resource\n");
109 return -ENXIO;
110 }
111
112 adsp->pa_sram = (phys_addr_t)mmio->start;
113 adsp->sramsize = resource_size(mmio);
114 if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) {
115 dev_err(dev, "adsp SRAM(%#x) is not enough for share\n",
116 adsp->sramsize);
117 return -EINVAL;
118 }
119
120 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
121
122 return ret;
123 }
124
125 static int adsp_sram_power_on(struct device *dev, bool on)
126 {
127 void __iomem *va_dspsysreg;
128 u32 srampool_con;
129
130 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
131 if (!va_dspsysreg) {
132 dev_err(dev, "failed to ioremap sram pool base %#x\n",
133 ADSP_SRAM_POOL_CON);
134 return -ENOMEM;
135 }
136
137 srampool_con = readl(va_dspsysreg);
138 if (on)
139 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
140 else
141 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
142
143 iounmap(va_dspsysreg);
144 return 0;
145 }
146
147 /* Init the basic DSP DRAM address */
148 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
149 {
150 void __iomem *vaddr_emi_map;
151 int offset;
152
153 if (!adsp)
154 return -ENXIO;
155
156 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
157 if (!vaddr_emi_map) {
158 dev_err(dev, "failed to ioremap emi map base %#x\n",
159 DSP_EMI_MAP_ADDR);
160 return -ENOMEM;
161 }
162
163 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
164 adsp->dram_offset = offset;
165 offset >>= DRAM_REMAP_SHIFT;
> 166 dev_dbg(dev, "adsp->pa_dram %llx, offset %#x\n", adsp->pa_dram, offset);
167 writel(offset, vaddr_emi_map);
168 if (offset != readl(vaddr_emi_map)) {
169 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
170 return -EIO;
171 }
172
173 return 0;
174 }
175
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months
[ammarfaizi2-block:google/android/kernel/common/android13-5.15 2757/2766] arch/arm64/kvm/arm.c:2011:46: error: 'smccc_trng_available' undeclared
by kernel test robot
tree: https://github.com/ammarfaizi2/linux-block google/android/kernel/common/android13-5.15
head: 9c25e5d6f58362a8ff78327664a2e3c2a538009f
commit: 888643ea37b504cb32afdd6430698d1e92a79a71 [2757/2766] ANDROID: KVM: arm64: relay entropy requests from protected guests directly to secure
config: arm64-buildonly-randconfig-r006-20220116 (https://download.01.org/0day-ci/archive/20220118/202201181042.DbgIXpRm-lk...)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/ammarfaizi2/linux-block/commit/888643ea37b504cb32afdd6...
git remote add ammarfaizi2-block https://github.com/ammarfaizi2/linux-block
git fetch --no-tags ammarfaizi2-block google/android/kernel/common/android13-5.15
git checkout 888643ea37b504cb32afdd6430698d1e92a79a71
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
arch/arm64/kvm/arm.c: In function 'kvm_hyp_init_protection':
>> arch/arm64/kvm/arm.c:2011:46: error: 'smccc_trng_available' undeclared (first use in this function)
2011 | kvm_nvhe_sym(smccc_trng_available) = smccc_trng_available;
| ^~~~~~~~~~~~~~~~~~~~
arch/arm64/kvm/arm.c:2011:46: note: each undeclared identifier is reported only once for each function it appears in
vim +/smccc_trng_available +2011 arch/arm64/kvm/arm.c
1997
1998 static int kvm_hyp_init_protection(u32 hyp_va_bits)
1999 {
2000 void *addr = phys_to_virt(hyp_mem_base);
2001 int ret;
2002
2003 kvm_nvhe_sym(id_aa64pfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2004 kvm_nvhe_sym(id_aa64pfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
2005 kvm_nvhe_sym(id_aa64isar0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR0_EL1);
2006 kvm_nvhe_sym(id_aa64isar1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
2007 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
2008 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2009 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);
2010 kvm_nvhe_sym(__icache_flags) = __icache_flags;
> 2011 kvm_nvhe_sym(smccc_trng_available) = smccc_trng_available;
2012
2013 ret = create_hyp_mappings(addr, addr + hyp_mem_size, PAGE_HYP);
2014 if (ret)
2015 return ret;
2016
2017 ret = init_stage2_iommu();
2018 if (ret < 0)
2019 return ret;
2020
2021 ret = do_pkvm_init(hyp_va_bits, (enum kvm_iommu_driver)ret);
2022 if (ret)
2023 return ret;
2024
2025 free_hyp_pgds();
2026
2027 return 0;
2028 }
2029
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months
[ammarfaizi2-block:dhowells/linux-fs/netfs-lib 21/24] fs/netfs/read_helper.c:971:14: warning: variable 'folio' is uninitialized when used here
by kernel test robot
tree: https://github.com/ammarfaizi2/linux-block dhowells/linux-fs/netfs-lib
head: e450b62f32df4384c141a6a382811b3fe5723bad
commit: 814cca7df840c441b1ac007bcb3eb8bfaeacb13f [21/24] cifs: Support fscache rewrite
config: arm-s3c2410_defconfig (https://download.01.org/0day-ci/archive/20220118/202201180713.iy4mum5Q-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 5f782d25a742302d25ef3c8b84b54f7483c2deb9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/ammarfaizi2/linux-block/commit/814cca7df840c441b1ac007...
git remote add ammarfaizi2-block https://github.com/ammarfaizi2/linux-block
git fetch --no-tags ammarfaizi2-block dhowells/linux-fs/netfs-lib
git checkout 814cca7df840c441b1ac007bcb3eb8bfaeacb13f
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash fs/netfs/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
>> fs/netfs/read_helper.c:971:14: warning: variable 'folio' is uninitialized when used here [-Wuninitialized]
folio_put(folio);
^~~~~
fs/netfs/read_helper.c:920:21: note: initialize the variable 'folio' to silence this warning
struct folio *folio;
^
= NULL
fs/netfs/read_helper.c:1267:7: error: implicit declaration of function 'netfs_is_cache_enabled' [-Werror,-Wimplicit-function-declaration]
if (!netfs_is_cache_enabled(ctx) &&
^
1 warning and 1 error generated.
vim +/folio +971 fs/netfs/read_helper.c
e6b340ed3634bb David Howells 2021-07-09 935
e6b340ed3634bb David Howells 2021-07-09 936 ret = netfs_rreq_add_folios_to_buffer(rreq, want_index, have_index - 1,
e6b340ed3634bb David Howells 2021-07-09 937 gfp_mask);
e6b340ed3634bb David Howells 2021-07-09 938 if (ret < 0)
e6b340ed3634bb David Howells 2021-07-09 939 return ret;
e6b340ed3634bb David Howells 2021-07-09 940 have_folios += have_index - want_index;
e6b340ed3634bb David Howells 2021-07-09 941
e6b340ed3634bb David Howells 2021-07-09 942 ret = netfs_rreq_add_folios_to_buffer(rreq, have_index + have_folios,
e6b340ed3634bb David Howells 2021-07-09 943 want_index + want_folios - 1,
e6b340ed3634bb David Howells 2021-07-09 944 gfp_mask);
e6b340ed3634bb David Howells 2021-07-09 945 if (ret < 0)
e6b340ed3634bb David Howells 2021-07-09 946 return ret;
e6b340ed3634bb David Howells 2021-07-09 947
e6b340ed3634bb David Howells 2021-07-09 948 /* Transfer the folios proposed by the VM into the buffer and take refs
e6b340ed3634bb David Howells 2021-07-09 949 * on them. The locks will be dropped in netfs_rreq_unlock().
e6b340ed3634bb David Howells 2021-07-09 950 */
e6b340ed3634bb David Howells 2021-07-09 951 if (ractl) {
e6b340ed3634bb David Howells 2021-07-09 952 while ((folio = readahead_folio(ractl))) {
e6b340ed3634bb David Howells 2021-07-09 953 folio_get(folio);
e6b340ed3634bb David Howells 2021-07-09 954 if (folio == keep)
e6b340ed3634bb David Howells 2021-07-09 955 folio_get(folio);
e6b340ed3634bb David Howells 2021-07-09 956 ret = xa_insert_set_mark(&rreq->buffer,
e6b340ed3634bb David Howells 2021-07-09 957 folio_index(folio), folio,
e6b340ed3634bb David Howells 2021-07-09 958 XA_MARK_0, gfp_mask);
e6b340ed3634bb David Howells 2021-07-09 959 if (ret < 0) {
e6b340ed3634bb David Howells 2021-07-09 960 if (folio != keep)
e6b340ed3634bb David Howells 2021-07-09 961 folio_unlock(folio);
e6b340ed3634bb David Howells 2021-07-09 962 folio_put(folio);
e6b340ed3634bb David Howells 2021-07-09 963 return ret;
e6b340ed3634bb David Howells 2021-07-09 964 }
e6b340ed3634bb David Howells 2021-07-09 965 }
e6b340ed3634bb David Howells 2021-07-09 966 } else {
e6b340ed3634bb David Howells 2021-07-09 967 folio_get(keep);
e6b340ed3634bb David Howells 2021-07-09 968 ret = xa_insert_set_mark(&rreq->buffer, keep->index, keep,
e6b340ed3634bb David Howells 2021-07-09 969 XA_MARK_0, gfp_mask);
e6b340ed3634bb David Howells 2021-07-09 970 if (ret < 0) {
e6b340ed3634bb David Howells 2021-07-09 @971 folio_put(folio);
e6b340ed3634bb David Howells 2021-07-09 972 return ret;
e6b340ed3634bb David Howells 2021-07-09 973 }
e6b340ed3634bb David Howells 2021-07-09 974 }
e6b340ed3634bb David Howells 2021-07-09 975 return 0;
e6b340ed3634bb David Howells 2021-07-09 976 }
e6b340ed3634bb David Howells 2021-07-09 977
:::::: The code at line 971 was first introduced by commit
:::::: e6b340ed3634bb80396afb564c499eebdeff601f netfs: Use a buffer in netfs_read_request and add pages to it
:::::: TO: David Howells <dhowells(a)redhat.com>
:::::: CC: David Howells <dhowells(a)redhat.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
8 months