[kbuild-all] [omap:omap-for-v5.13/genpd-drop-legacy 38/45] dtbs_check: arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: interconnect@4ae00000: $nodename:0: 'interconnect@4ae00000' does not match

tree: https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git omap-for-v5.13/genpd-drop-legacy head: 569519de002fafde35f889a8ea0348eae6ccc20f commit: 9a75368b6426739e8b798592f084cb682d760568 [38/45] ARM: dts: Configure simple-pm-bus for dra7 l4_wkup compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce: make ARCH=arm dtbs_check If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; "dtcheck warnings: (new ones prefixed by >>)" arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compati ble': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg' : [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True , 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[179]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137] , [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max- div': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[150]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'c ompatible': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two' : True, 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[179]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [ [0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 't i,max-div': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[150]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revb1.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'co mpatible': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[178]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[ 0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti ,max-div': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[150]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-beagle-x15-revc.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compa tible': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 're g': [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': Tr ue, 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[176]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]] , 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [13 7], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,ma x-div': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[149]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am5729-beagleboneai.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compa tible': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 're g': [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': Tr ue, 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[174]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]] , 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [13 7], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,ma x-div': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[149]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-cl-som-am57x.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatib le': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[180]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], ' compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-d iv': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[151]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am57xx-sbc-am57x.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am572x-idk.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [ 'ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460 ]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phan dle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[181]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compat ible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138] , [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-div': [ [64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[152]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am572x-idk.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am571x-idk.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [ 'ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460 ]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phan dle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[184]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compat ible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138] , [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-div': [ [64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[152]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am571x-idk.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/am574x-idk.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[106], [107], [108], [109], [110], [111], [112]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[21]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[280]], 'phandle': [[114]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[114], [82]], 'reg': [[276]], 'phandle': [[23]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[114], [82]], 'reg': [[268]], 'phandle': [[22]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[26]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[90]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [ 'ti,divider-clock'], 'clocks': [[115]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[116]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[26]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[148]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113], [82]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[113]], 'ti,max-div': [[64]], 'reg': [[460 ]], 'ti,index-power-of-two': True, 'phandle': [[126]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[37]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[44]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[118]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[133]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phan dle': [[120]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[120]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[181]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[79]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compat ible': ['ti,divider-clock'], 'clocks': [[123]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[143]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[124]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[144]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143], [144], [145]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140] , [141], [142], [143], [144], [145]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143], [144], [145]], 'reg': [[352]], 'phandle': [[80]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[21]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[55], [58]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[146]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[147]], 'ti,max-div': [ [64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[154]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [148]], 'reg': [[264]], 'phandle': [[87]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/am574x-idk.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/dra7-evm.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': ['t i,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460]] , 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phandl e': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[203]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compatib le': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-div': [[6 4]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[151]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra7-evm.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/dra72-evm.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [' ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [[460] ], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phand le': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[195]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compati ble': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-div': [[ 64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[151]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/dra72-evm-revc.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[104], [105], [106], [107], [108], [109], [110]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[17]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[280]], 'phandle': [[112]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[276]], 'phandle': [[19]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[112], [80]], 'reg': [[268]], 'phandle': [[18]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[88]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible ': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[114]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[22]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[146]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111], [80]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[111]], 'ti,max-div': [[64]], 'reg': [ [460]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[33]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[40]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, ' phandle': [[118]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[118]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[198]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[77]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'co mpatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [ 138], [139], [140], [141], [142], [143]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[123], [124], [125], [126], [127], [128], [129], [130], [131], [118], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143]], 'reg': [[352]], 'phandle': [[78]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[17]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[52], [55]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[145]], 'ti,max-div ': [[64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[17]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[151]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [111]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[17], [146]], 'reg': [[264]], 'phandle': [[85]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra72-evm-revc.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/dra71-evm.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[103], [104], [105], [106], [107], [108], [109]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[16]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [110]], 'reg': [[280]], 'phandle': [[111]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[111], [79]], 'reg': [[276]], 'phandle': [[18]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[111], [79]], 'reg': [[268]], 'phandle': [[17]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[87]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [' ti,divider-clock'], 'clocks': [[112]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[113]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[113]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[145]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[16]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [110], [79]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[16]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[122]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[110]], 'ti,max-div': [[64]], 'reg': [[460] ], 'ti,index-power-of-two': True, 'phandle': [[123]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[124]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[32]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[126]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[39]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[128]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[115]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[130]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phand le': [[117]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[117]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[196]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[76]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[135]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[118]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[136]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[16]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[137]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compati ble': ['ti,divider-clock'], 'clocks': [[120]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[16]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[122], [123], [124], [125], [126], [127], [128], [129], [130], [117], [131], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[122], [123], [124], [125], [126], [127], [128], [129], [130], [117], [131], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[122], [123], [124], [125], [126], [127], [128], [129], [130], [117], [131], [132], [133], [134], [135], [136], [137], [138], [139], [140], [141], [142]], 'reg': [[352]], 'phandle': [[77]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[16]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[51], [54]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [110]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[143]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[144]], 'ti,max-div': [[ 64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[114]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[16]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[150]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [110]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [110]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[16], [145]], 'reg': [[264]], 'phandle': [[84]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra71-evm.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: -- arch/arm/boot/dts/dra76-evm.dt.yaml: l4per-clkctrl@28: 'clocks' is a dependency of 'assigned-clocks' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/clock/clock.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: phy@4000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: phy@5000: 'phy-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: segment@100000: $nodename:0: 'segment@100000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: segment@200000: $nodename:0: 'segment@200000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml 'clocks' is a required property 'power-domains' is a required property From schema: Documentation/devicetree/bindings/bus/simple-pm-bus.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: prm@0: $nodename:0: 'prm@0' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: prm@0: clocks: {'type': 'object'} is not allowed for {'#address-cells': [[1]], '#size-cells': [[0]], 'sys_clkin1@110': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[106], [107], [108], [109], [110], [111], [112]], 'reg': [[272]], 'ti,index-starts-at-one': True, 'phandle': [[21]]}, 'abe_dpll_sys_clk_mux@118': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[280]], 'phandle': [[114]]}, 'abe_dpll_bypass_clk_mux@114': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[114], [82]], 'reg': [[276]], 'phandle': [[23]]}, 'abe_dpll_clk_mux@10c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[114], [82]], 'reg': [[268]], 'phandle': [[22]]}, 'abe_24m_fclk@11c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[26]], 'reg': [[284]], 'ti,dividers': [[8], [16]], 'phandle': [[90]]}, 'aess_fclk@178': {'#clock-cells': [[0]], 'compatible': [' ti,divider-clock'], 'clocks': [[115]], 'reg': [[376]], 'ti,max-div': [[2]], 'phandle': [[116]]}, 'abe_giclk_div@174': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[116]], 'reg': [[372]], 'ti,max-div': [[2]]}, 'abe_lp_clk_div@1d8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[26]], 'reg': [[472]], 'ti,dividers': [[16], [32]], 'phandle': [[148]]}, 'abe_sys_clk_div@120': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[288]], 'ti,max-div': [[2]]}, 'adc_gfclk_mux@1dc': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113], [82]], 'reg': [[476]]}, 'sys_clk1_dclk_div@1c8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[456]], 'ti,index-power-of-two': True, 'phandle': [[125]]}, 'sys_clk2_dclk_div@1cc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[113]], 'ti,max-div': [[64]], 'reg': [[460] ], 'ti,index-power-of-two': True, 'phandle': [[126]]}, 'per_abe_x1_dclk_div@1bc': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[444]], 'ti,index-power-of-two': True, 'phandle': [[127]]}, 'dsp_gclk_div@18c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[37]], 'ti,max-div': [[64]], 'reg': [[396]], 'ti,index-power-of-two': True, 'phandle': [[129]]}, 'gpu_dclk@1a0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[44]], 'ti,max-div': [[64]], 'reg': [[416]], 'ti,index-power-of-two': True, 'phandle': [[131]]}, 'emif_phy_dclk_div@190': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[118]], 'ti,max-div': [[64]], 'reg': [[400]], 'ti,index-power-of-two': True, 'phandle': [[133]]}, 'gmac_250m_dclk_div@19c': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[119]], 'ti,max-div': [[64]], 'reg': [[412]], 'ti,index-power-of-two': True, 'phand le': [[120]]}, 'gmac_main_clk': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[120]], 'clock-mult': [[1]], 'clock-div': [[2]], 'phandle': [[190]]}, 'l3init_480m_dclk_div@1ac': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[79]], 'ti,max-div': [[64]], 'reg': [[428]], 'ti,index-power-of-two': True, 'phandle': [[138]]}, 'usb_otg_dclk_div@184': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[121]], 'ti,max-div': [[64]], 'reg': [[388]], 'ti,index-power-of-two': True, 'phandle': [[139]]}, 'sata_dclk_div@1c0': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[448]], 'ti,index-power-of-two': True, 'phandle': [[140]]}, 'pcie2_dclk_div@1b8': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[122]], 'ti,max-div': [[64]], 'reg': [[440]], 'ti,index-power-of-two': True, 'phandle': [[141]]}, 'pcie_dclk_div@1b4': {'#clock-cells': [[0]], 'compati ble': ['ti,divider-clock'], 'clocks': [[123]], 'ti,max-div': [[64]], 'reg': [[436]], 'ti,index-power-of-two': True, 'phandle': [[142]]}, 'emu_dclk_div@194': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'ti,max-div': [[64]], 'reg': [[404]], 'ti,index-power-of-two': True, 'phandle': [[143]]}, 'secure_32k_dclk_div@1c4': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[124]], 'ti,max-div': [[64]], 'reg': [[452]], 'ti,index-power-of-two': True, 'phandle': [[144]]}, 'clkoutmux0_clk_mux@158': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143], [144], [145]], 'reg': [[344]]}, 'clkoutmux1_clk_mux@15c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143], [144], [145]], 'reg': [[348]]}, 'clkoutmux2_clk_mux@160': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[125], [126], [127], [128], [129], [130], [131], [132], [133], [120], [134], [135], [136], [137], [138], [139], [140], [141], [142], [143], [144], [145]], 'reg': [[352]], 'phandle': [[80]]}, 'custefuse_sys_gfclk_div': {'#clock-cells': [[0]], 'compatible': ['fixed-factor-clock'], 'clocks': [[21]], 'clock-mult': [[1]], 'clock-div': [[2]]}, 'eve_clk@180': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[55], [58]], 'reg': [[384]]}, 'hdmi_dpll_clk_mux@164': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[356]]}, 'mlb_clk@134': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[146]], 'ti,max-div': [[64]], 'reg': [[308]], 'ti,index-power-of-two': True}, 'mlbp_clk@130': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[147]], 'ti,max-div': [[ 64]], 'reg': [[304]], 'ti,index-power-of-two': True}, 'per_abe_x1_gfclk2_div@138': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[117]], 'ti,max-div': [[64]], 'reg': [[312]], 'ti,index-power-of-two': True}, 'timer_sys_clk_div@144': {'#clock-cells': [[0]], 'compatible': ['ti,divider-clock'], 'clocks': [[21]], 'reg': [[324]], 'ti,max-div': [[2]], 'phandle': [[151]]}, 'video1_dpll_clk_mux@168': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[360]]}, 'video2_dpll_clk_mux@16c': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [113]], 'reg': [[364]]}, 'wkupaon_iclk_mux@108': {'#clock-cells': [[0]], 'compatible': ['ti,mux-clock'], 'clocks': [[21], [148]], 'reg': [[264]], 'phandle': [[87]]}} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: prm@0: clockdomains: {'type': 'object'} is not allowed for {} From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/simple-bus.yaml arch/arm/boot/dts/dra76-evm.dt.yaml: scm_conf@0: compatible: 'anyOf' conditional failed, one must be fixed: --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org