[kbuild-all] [xlnx:xlnx_rebase_v5.10 917/1761] drivers/misc/jesd204b/jesd_phy.c:97:6: warning: variable 'pll' set but not used

tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.10 head: e14d4574ca81a569ee6d07e03271f2ae2dad38e4 commit: 99ac99c4c6134cc12abee1f845a897eafb125ba3 [917/1761] misc: jesd204b driver support config: m68k-randconfig-r014-20210812 (attached as .config) compiler: m68k-linux-gcc (GCC) 10.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/Xilinx/linux-xlnx/commit/99ac99c4c6134cc12abee1f845a89... git remote add xlnx https://github.com/Xilinx/linux-xlnx git fetch --no-tags xlnx xlnx_rebase_v5.10 git checkout 99ac99c4c6134cc12abee1f845a897eafb125ba3 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=m68k If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/misc/jesd204b/jesd_phy.c: In function 'read_plls': 97 | int pll = st->pll; | ^~~ drivers/misc/jesd204b/jesd_phy.c: At top level: 172 | void jesd204_phy_set_speed(struct jesd204b_phy_state *st, u32 band) | ^~~~~~~~~~~~~~~~~~~~~ vim +/pll +97 drivers/misc/jesd204b/jesd_phy.c 93 94 static void read_plls(struct jesd204b_phy_state *st) 95 { 96 int i; 98 u32 no_of_common_drp_interfaces = 1; 99 100 if (st->pll == CPLL) 101 no_of_common_drp_interfaces = jesd204b_phy_read( 102 st, NR_TRANS_DRP_INTERFACES); 103 else 104 no_of_common_drp_interfaces = jesd204b_phy_read( 105 st, NR_COMMON_DRP_INTERFACES); 106 107 for (i = 0; i < no_of_common_drp_interfaces; i++) { 108 jesd204b_phy_write(st, CHANNEL_XCVR_SEL, i); 109 pll = jesd204b_phy_read(st, CHANNEL_XCVR_TXPLL); 110 pll = jesd204b_phy_read(st, CHANNEL_XCVR_RXPLL); 111 } 112 } 113 114 static void configure_plls(struct jesd204b_phy_state *st, u32 pll) 115 { 116 int i; 117 u32 no_of_common_drp_interfaces; 118 119 if (pll == CPLL) 120 no_of_common_drp_interfaces = jesd204b_phy_read( 121 st, NR_TRANS_DRP_INTERFACES); 122 else 123 no_of_common_drp_interfaces = jesd204b_phy_read( 124 st, NR_COMMON_DRP_INTERFACES); 125 126 for (i = 0; i < no_of_common_drp_interfaces; i++) { 127 jesd204b_phy_write(st, CHANNEL_XCVR_SEL, i); 128 jesd204b_phy_write(st, CHANNEL_XCVR_TXPLL, pll); 129 jesd204b_phy_write(st, CHANNEL_XCVR_RXPLL, pll); 130 } 131 } 132 133 static void configure_channel_drp(struct jesd204b_phy_state *st, u32 setting) 134 { 135 u32 i, j, addr, temp, no_of_common_drp_interfaces; 136 u32 no_channel_drp_reg = GTX7S_QPLL_NUM_CHANNEL_DRP_REGS; 137 138 no_of_common_drp_interfaces = jesd204b_phy_read( 139 st, NR_TRANS_DRP_INTERFACES); 140 141 if (st->pll == CPLL) 142 no_channel_drp_reg = GTX7S_CPLL_NUM_CHANNEL_DRP_REGS; 143 for (i = 0; i < no_of_common_drp_interfaces; i++) { 144 jesd204b_phy_write(st, CHANNEL_DRP_BASE, i); 145 for (j = 0; j < no_channel_drp_reg; j++) { 146 /* Get the register address */ 147 if (st->pll == QPLL) { 148 addr = get_gtx7s_qpll_address_lut(j); 149 150 /* Read the register */ 151 temp = read_channel_drp_reg(st, addr); 152 153 temp &= (0xFFFF ^ (get_gtx7s_qpll_mask_lut(j))); 154 temp |= ((get_gtx7s_qpll_param_lut(j, setting) 155 << get_gtx7s_qpll_offset_lut(j)) 156 & get_gtx7s_qpll_mask_lut(j)); 157 } else { 158 addr = get_gtx7s_cpll_address_lut(j); 159 160 temp = read_channel_drp_reg(st, addr); 161 162 temp &= (0xFFFF ^ (get_gtx7s_cpll_mask_lut(j))); 163 temp |= ((get_gtx7s_cpll_param_lut(j, setting) 164 << get_gtx7s_cpll_offset_lut(j)) 165 & get_gtx7s_cpll_mask_lut(j)); 166 } 167 write_channel_drp_reg(st, addr, temp); 168 } 169 } 170 } 171 173 { 174 /* make sure we have the correct PLL's selected. */ 175 configure_channel_drp(st, band); 176 } 177 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org