10:01 a.m.
tree: git://people.freedesktop.org/~mlankhorst/linux xe
head: 4bc3039b4403c76a13d58f7ac1f7c07dca6f88d8
commit: 0fc4361f4fc10e980acdb7328ad17d66aa1c3644 [37/165] MOAR
config: i386-allyesconfig
(https://download.01.org/0day-ci/archive/20220126/202201260746.o0wAH4uG-lk...)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
git remote add mlankhorst git://people.freedesktop.org/~mlankhorst/linux
git fetch --no-tags mlankhorst xe
git checkout 0fc4361f4fc10e980acdb7328ad17d66aa1c3644
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
> drivers/gpu/drm/xe/xe_irq.c:30:6: error: no previous prototype
for 'gen11_gt_irq_reset' [-Werror=missing-prototypes]
30 | void
gen11_gt_irq_reset(struct xe_device *xe)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/gen11_gt_irq_reset +30 drivers/gpu/drm/xe/xe_irq.c
29
30 void gen11_gt_irq_reset(struct xe_device *xe)
31 {
32 /* Disable RCS, BCS, VCS and VECS class engines. */
33 xe_mmio_write32(xe, GEN11_RENDER_COPY_INTR_ENABLE.reg, 0);
34 xe_mmio_write32(xe, GEN11_VCS_VECS_INTR_ENABLE.reg, 0);
35
36 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
37 xe_mmio_write32(xe, GEN11_RCS0_RSVD_INTR_MASK.reg, ~0);
38 xe_mmio_write32(xe, GEN11_BCS_RSVD_INTR_MASK.reg, ~0);
39 xe_mmio_write32(xe, GEN11_VCS0_VCS1_INTR_MASK.reg, ~0);
40 xe_mmio_write32(xe, GEN11_VCS2_VCS3_INTR_MASK.reg, ~0);
41 // if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
42 // xe_mmio_write32(xe, GEN12_VCS4_VCS5_INTR_MASK.reg, ~0);
43 // if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
44 // xe_mmio_write32(xe, GEN12_VCS6_VCS7_INTR_MASK.reg, ~0);
45 xe_mmio_write32(xe, GEN11_VECS0_VECS1_INTR_MASK.reg, ~0);
46 // if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
47 // xe_mmio_write32(xe, GEN12_VECS2_VECS3_INTR_MASK.reg, ~0);
48
49 xe_mmio_write32(xe, GEN11_GPM_WGBOXPERF_INTR_ENABLE.reg, 0);
50 xe_mmio_write32(xe, GEN11_GPM_WGBOXPERF_INTR_MASK.reg, ~0);
51 xe_mmio_write32(xe, GEN11_GUC_SG_INTR_ENABLE.reg, 0);
52 xe_mmio_write32(xe, GEN11_GUC_SG_INTR_MASK.reg, ~0);
53 }
54
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org