[kbuild-all] [hnaz-linux-mm:master 380/523] arch/riscv/kernel/kgdb.c:47:5: warning: no previous prototype for 'decode_register_index'

Hi Andrew, First bad commit (maybe != root cause): tree: https://github.com/hnaz/linux-mm master head: 2bbf0589bfeb27800c730b76eacf34528eee5418 commit: 91cd0b1b65c463042fdeb4ab5ffcb64ae43179cf [380/523] linux-next-rejects config: riscv-allyesconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 91cd0b1b65c463042fdeb4ab5ffcb64ae43179cf # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): 47 | int decode_register_index(unsigned long opcode, int offset) | ^~~~~~~~~~~~~~~~~~~~~ 52 | int decode_register_index_short(unsigned long opcode, int offset) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | int get_step_address(struct pt_regs *regs, unsigned long *next_addr) | ^~~~~~~~~~~~~~~~ 139 | int do_single_step(struct pt_regs *regs) | ^~~~~~~~~~~~~~ 276 | void kgdb_arch_handle_qxfer_pkt(char *remcom_in_buffer, | ^~~~~~~~~~~~~~~~~~~~~~~~~~ 323 | int kgdb_riscv_kgdbbreak(unsigned long addr) | ^~~~~~~~~~~~~~~~~~~~ In file included from arch/riscv/include/asm/kgdb.h:109, from include/linux/kgdb.h:20, from arch/riscv/kernel/kgdb.c:9: arch/riscv/include/asm/gdb_xml.h:7:19: warning: 'riscv_gdb_stub_feature' defined but not used [-Wunused-const-variable=] 7 | static const char riscv_gdb_stub_feature[64] = | ^~~~~~~~~~~~~~~~~~~~~~ vim +/decode_register_index +47 arch/riscv/kernel/kgdb.c 7426ea952ca32f Andrew Morton 2020-05-16 46 7426ea952ca32f Andrew Morton 2020-05-16 @47 int decode_register_index(unsigned long opcode, int offset) 7426ea952ca32f Andrew Morton 2020-05-16 48 { 7426ea952ca32f Andrew Morton 2020-05-16 49 return (opcode >> offset) & 0x1F; 7426ea952ca32f Andrew Morton 2020-05-16 50 } 7426ea952ca32f Andrew Morton 2020-05-16 51 7426ea952ca32f Andrew Morton 2020-05-16 @52 int decode_register_index_short(unsigned long opcode, int offset) 7426ea952ca32f Andrew Morton 2020-05-16 53 { 7426ea952ca32f Andrew Morton 2020-05-16 54 return ((opcode >> offset) & 0x7) + 8; 7426ea952ca32f Andrew Morton 2020-05-16 55 } 7426ea952ca32f Andrew Morton 2020-05-16 56 7426ea952ca32f Andrew Morton 2020-05-16 57 /* Calculate the new address for after a step */ 7426ea952ca32f Andrew Morton 2020-05-16 @58 int get_step_address(struct pt_regs *regs, unsigned long *next_addr) 7426ea952ca32f Andrew Morton 2020-05-16 59 { 7426ea952ca32f Andrew Morton 2020-05-16 60 unsigned long pc = regs->epc; 7426ea952ca32f Andrew Morton 2020-05-16 61 unsigned long *regs_ptr = (unsigned long *)regs; 7426ea952ca32f Andrew Morton 2020-05-16 62 unsigned int rs1_num, rs2_num; 7426ea952ca32f Andrew Morton 2020-05-16 63 int op_code; 7426ea952ca32f Andrew Morton 2020-05-16 64 7426ea952ca32f Andrew Morton 2020-05-16 65 if (probe_kernel_address((void *)pc, op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 66 return -EINVAL; 7426ea952ca32f Andrew Morton 2020-05-16 67 if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) { 7426ea952ca32f Andrew Morton 2020-05-16 68 if (is_c_jalr_insn(op_code) || is_c_jr_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 69 rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 70 *next_addr = regs_ptr[rs1_num]; 7426ea952ca32f Andrew Morton 2020-05-16 71 } else if (is_c_j_insn(op_code) || is_c_jal_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 72 *next_addr = EXTRACT_RVC_J_IMM(op_code) + pc; 7426ea952ca32f Andrew Morton 2020-05-16 73 } else if (is_c_beqz_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 74 rs1_num = decode_register_index_short(op_code, 7426ea952ca32f Andrew Morton 2020-05-16 75 RVC_C1_RS1_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 76 if (!rs1_num || regs_ptr[rs1_num] == 0) 7426ea952ca32f Andrew Morton 2020-05-16 77 *next_addr = EXTRACT_RVC_B_IMM(op_code) + pc; 7426ea952ca32f Andrew Morton 2020-05-16 78 else 7426ea952ca32f Andrew Morton 2020-05-16 79 *next_addr = pc + 2; 7426ea952ca32f Andrew Morton 2020-05-16 80 } else if (is_c_bnez_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 81 rs1_num = 7426ea952ca32f Andrew Morton 2020-05-16 82 decode_register_index_short(op_code, RVC_C1_RS1_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 83 if (rs1_num && regs_ptr[rs1_num] != 0) 7426ea952ca32f Andrew Morton 2020-05-16 84 *next_addr = EXTRACT_RVC_B_IMM(op_code) + pc; 7426ea952ca32f Andrew Morton 2020-05-16 85 else 7426ea952ca32f Andrew Morton 2020-05-16 86 *next_addr = pc + 2; 7426ea952ca32f Andrew Morton 2020-05-16 87 } else { 7426ea952ca32f Andrew Morton 2020-05-16 88 *next_addr = pc + 2; 7426ea952ca32f Andrew Morton 2020-05-16 89 } 7426ea952ca32f Andrew Morton 2020-05-16 90 } else { 7426ea952ca32f Andrew Morton 2020-05-16 91 if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) { 7426ea952ca32f Andrew Morton 2020-05-16 92 bool result = false; 7426ea952ca32f Andrew Morton 2020-05-16 93 long imm = EXTRACT_BTYPE_IMM(op_code); 7426ea952ca32f Andrew Morton 2020-05-16 94 unsigned long rs1_val = 0, rs2_val = 0; 7426ea952ca32f Andrew Morton 2020-05-16 95 7426ea952ca32f Andrew Morton 2020-05-16 96 rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 97 rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 98 if (rs1_num) 7426ea952ca32f Andrew Morton 2020-05-16 99 rs1_val = regs_ptr[rs1_num]; 7426ea952ca32f Andrew Morton 2020-05-16 100 if (rs2_num) 7426ea952ca32f Andrew Morton 2020-05-16 101 rs2_val = regs_ptr[rs2_num]; 7426ea952ca32f Andrew Morton 2020-05-16 102 7426ea952ca32f Andrew Morton 2020-05-16 103 if (is_beq_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 104 result = (rs1_val == rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 105 else if (is_bne_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 106 result = (rs1_val != rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 107 else if (is_blt_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 108 result = 7426ea952ca32f Andrew Morton 2020-05-16 109 ((long)rs1_val < 7426ea952ca32f Andrew Morton 2020-05-16 110 (long)rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 111 else if (is_bge_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 112 result = 7426ea952ca32f Andrew Morton 2020-05-16 113 ((long)rs1_val >= 7426ea952ca32f Andrew Morton 2020-05-16 114 (long)rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 115 else if (is_bltu_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 116 result = (rs1_val < rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 117 else if (is_bgeu_insn(op_code)) 7426ea952ca32f Andrew Morton 2020-05-16 118 result = (rs1_val >= rs2_val) ? true : false; 7426ea952ca32f Andrew Morton 2020-05-16 119 if (result) 7426ea952ca32f Andrew Morton 2020-05-16 120 *next_addr = imm + pc; 7426ea952ca32f Andrew Morton 2020-05-16 121 else 7426ea952ca32f Andrew Morton 2020-05-16 122 *next_addr = pc + 4; 7426ea952ca32f Andrew Morton 2020-05-16 123 } else if (is_jal_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 124 *next_addr = EXTRACT_JTYPE_IMM(op_code) + pc; 7426ea952ca32f Andrew Morton 2020-05-16 125 } else if (is_jalr_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 126 rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF); 7426ea952ca32f Andrew Morton 2020-05-16 127 if (rs1_num) 7426ea952ca32f Andrew Morton 2020-05-16 128 *next_addr = ((unsigned long *)regs)[rs1_num]; 7426ea952ca32f Andrew Morton 2020-05-16 129 *next_addr += EXTRACT_ITYPE_IMM(op_code); 7426ea952ca32f Andrew Morton 2020-05-16 130 } else if (is_sret_insn(op_code)) { 7426ea952ca32f Andrew Morton 2020-05-16 131 *next_addr = pc; 7426ea952ca32f Andrew Morton 2020-05-16 132 } else { 7426ea952ca32f Andrew Morton 2020-05-16 133 *next_addr = pc + 4; 7426ea952ca32f Andrew Morton 2020-05-16 134 } 7426ea952ca32f Andrew Morton 2020-05-16 135 } 7426ea952ca32f Andrew Morton 2020-05-16 136 return 0; 7426ea952ca32f Andrew Morton 2020-05-16 137 } 7426ea952ca32f Andrew Morton 2020-05-16 138 7426ea952ca32f Andrew Morton 2020-05-16 @139 int do_single_step(struct pt_regs *regs) 7426ea952ca32f Andrew Morton 2020-05-16 140 { 7426ea952ca32f Andrew Morton 2020-05-16 141 /* Determine where the target instruction will send us to */ 7426ea952ca32f Andrew Morton 2020-05-16 142 unsigned long addr = 0; 7426ea952ca32f Andrew Morton 2020-05-16 143 int error = get_step_address(regs, &addr); 7426ea952ca32f Andrew Morton 2020-05-16 144 7426ea952ca32f Andrew Morton 2020-05-16 145 if (error) 7426ea952ca32f Andrew Morton 2020-05-16 146 return error; 7426ea952ca32f Andrew Morton 2020-05-16 147 7426ea952ca32f Andrew Morton 2020-05-16 148 /* Store the op code in the stepped address */ 7426ea952ca32f Andrew Morton 2020-05-16 149 error = probe_kernel_address((void *)addr, stepped_opcode); 7426ea952ca32f Andrew Morton 2020-05-16 150 if (error) 7426ea952ca32f Andrew Morton 2020-05-16 151 return error; 7426ea952ca32f Andrew Morton 2020-05-16 152 7426ea952ca32f Andrew Morton 2020-05-16 153 stepped_address = addr; 7426ea952ca32f Andrew Morton 2020-05-16 154 7426ea952ca32f Andrew Morton 2020-05-16 155 /* Replace the op code with the break instruction */ 7426ea952ca32f Andrew Morton 2020-05-16 156 error = probe_kernel_write((void *)stepped_address, 7426ea952ca32f Andrew Morton 2020-05-16 157 arch_kgdb_ops.gdb_bpt_instr, 7426ea952ca32f Andrew Morton 2020-05-16 158 BREAK_INSTR_SIZE); 7426ea952ca32f Andrew Morton 2020-05-16 159 /* Flush and return */ 7426ea952ca32f Andrew Morton 2020-05-16 160 if (!error) { 7426ea952ca32f Andrew Morton 2020-05-16 161 flush_icache_range(addr, addr + BREAK_INSTR_SIZE); 7426ea952ca32f Andrew Morton 2020-05-16 162 kgdb_single_step = 1; 7426ea952ca32f Andrew Morton 2020-05-16 163 atomic_set(&kgdb_cpu_doing_single_step, 7426ea952ca32f Andrew Morton 2020-05-16 164 raw_smp_processor_id()); 7426ea952ca32f Andrew Morton 2020-05-16 165 } else { 7426ea952ca32f Andrew Morton 2020-05-16 166 stepped_address = 0; 7426ea952ca32f Andrew Morton 2020-05-16 167 stepped_opcode = 0; 7426ea952ca32f Andrew Morton 2020-05-16 168 } 7426ea952ca32f Andrew Morton 2020-05-16 169 return error; 7426ea952ca32f Andrew Morton 2020-05-16 170 } 7426ea952ca32f Andrew Morton 2020-05-16 171 :::::: The code at line 47 was first introduced by commit :::::: 7426ea952ca32fa58beff5efbbc8ee0d8f84aadc linux-next :::::: TO: Andrew Morton <akpm(a)linux-foundation.org&gt; :::::: CC: Johannes Weiner <hannes(a)cmpxchg.org&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org