2:46 a.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git preview
head: e675fabdbbcdb6e32dba688a20fb0bd42e0e2d5d
commit: 2b7a34a480122fb652df99554f6d59c5d9f3ef24 [34/53] cxl/core: Generalize dport
enumeration in the core
config: mips-randconfig-c004-20220120
(https://download.01.org/0day-ci/archive/20220122/202201222342.XT0vW1nO-lk...)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
7b3d30728816403d1fd73cc5082e9fb761262bce)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mips-linux-gnu
#
https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?id=2b...
git remote add cxl https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git
git fetch --no-tags cxl preview
git checkout 2b7a34a480122fb652df99554f6d59c5d9f3ef24
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir
ARCH=mips SHELL=/bin/bash drivers/cxl/core/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All error/warnings (new ones prefixed by >>):
> drivers/cxl/core/pci.c:48:31: error: use of undeclared identifier
'CXL_REGLOC_RBI_COMPONENT'
rc = cxl_find_regblock(pdev,
CXL_REGLOC_RBI_COMPONENT, &map);
^
> drivers/cxl/core/pci.c:55:8: error: implicit declaration of
function 'cxl_regmap_to_base' [-Werror,-Wimplicit-function-declaration]
cxl_regmap_to_base(pdev, &map));
^
> drivers/cxl/core/pci.c:76:5: warning: no previous prototype for
function 'devm_cxl_port_enumerate_dports' [-Wmissing-prototypes]
int
devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port)
^
drivers/cxl/core/pci.c:76:1: note: declare 'static' if the function is not
intended to be used outside of this translation unit
int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port)
^
static
1 warning and 2 errors generated.
vim +/CXL_REGLOC_RBI_COMPONENT +48 drivers/cxl/core/pci.c
24
25 static int match_add_dports(struct pci_dev *pdev, void *data)
26 {
27 struct cxl_walk_context *ctx = data;
28 struct cxl_port *port = ctx->port;
29 struct device *host = ctx->host;
30 struct pci_bus *bus = ctx->bus;
31 int type = pci_pcie_type(pdev);
32 struct cxl_register_map map;
33 int match_type = ctx->type;
34 struct cxl_dport *dport;
35 u32 lnkcap, port_num;
36 int rc;
37
38 if (pdev->bus != bus)
39 return 0;
40 if (!pci_is_pcie(pdev))
41 return 0;
42 if (type != match_type)
43 return 0;
44 if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
45 &lnkcap) != PCIBIOS_SUCCESSFUL)
46 return 0;
47
48 rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
49 if (rc)
50 dev_dbg(&port->dev, "failed to find component registers\n");
51
52 port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
53 cxl_device_lock(&port->dev);
54 dport = devm_cxl_add_dport(host, port, &pdev->dev, port_num,
55 cxl_regmap_to_base(pdev, &map));
56 cxl_device_unlock(&port->dev);
57 if (IS_ERR(dport)) {
58 ctx->error = PTR_ERR(dport);
59 return PTR_ERR(dport);
60 }
61 ctx->count++;
62
63 dev_dbg(&port->dev, "add dport%d: %s\n", port_num,
dev_name(&pdev->dev));
64
65 return 0;
66 }
67
68 /**
69 * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream
port
70 * @host: devm context
71 * @port: cxl_port whose ->uport is the upstream of dports to be enumerated
72 *
73 * Returns a positive number of dports enumerated or a negative error
74 * code.
75 */
76 int devm_cxl_port_enumerate_dports(struct device *host, struct
cxl_port *port)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org