[kbuild-all] [arm-platforms:hack/m1-aic 8/9] drivers/irqchip/irq-gic-v3.c:1743:2: error: implicit declaration of function 'set_handle_irq_entry'; did you mean

tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git hack/m1-aic head: a1e6adfab5efe54d01a22bf7e9c638f248140146 commit: 7fe8b45fa364a813f852e4374892652af346ff1e [8/9] [DO NOT MERGE] irqchip/gic-v3: Route SGI/PPI as FIQ config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/com... git remote add arm-platforms https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git git fetch --no-tags arm-platforms hack/m1-aic git checkout 7fe8b45fa364a813f852e4374892652af346ff1e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/irqchip/irq-gic-v3.c: In function 'gic_eoi_irq': drivers/irqchip/irq-gic-v3.c:534:3: error: implicit declaration of function 'write_sysreg_s'; did you mean 'write_sysreg'? [-Werror=implicit-function-declaration] 534 | write_sysreg_s(d->hwirq, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~ | write_sysreg drivers/irqchip/irq-gic-v3.c:534:28: error: 'SYS_ICC_EOIR0_EL1' undeclared (first use in this function) 534 | write_sysreg_s(d->hwirq, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c:534:28: note: each undeclared identifier is reported only once for each function it appears in drivers/irqchip/irq-gic-v3.c: In function 'gic_handle_fiq': drivers/irqchip/irq-gic-v3.c:686:10: error: implicit declaration of function 'read_sysreg_s'; did you mean 'read_sysreg'? [-Werror=implicit-function-declaration] 686 | irqnr = read_sysreg_s(SYS_ICC_IAR0_EL1); | ^~~~~~~~~~~~~ | read_sysreg drivers/irqchip/irq-gic-v3.c:686:24: error: 'SYS_ICC_IAR0_EL1' undeclared (first use in this function) 686 | irqnr = read_sysreg_s(SYS_ICC_IAR0_EL1); | ^~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c:704:25: error: 'SYS_ICC_EOIR0_EL1' undeclared (first use in this function) 704 | write_sysreg_s(irqnr, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c: In function 'gic_cpu_sys_reg_init': drivers/irqchip/irq-gic-v3.c:990:21: error: 'SYS_ICC_BPR0_EL1' undeclared (first use in this function); did you mean 'read_ICC_AP1R0_EL1'? 990 | write_sysreg_s(0, SYS_ICC_BPR0_EL1); | ^~~~~~~~~~~~~~~~ | read_ICC_AP1R0_EL1 drivers/irqchip/irq-gic-v3.c:1038:21: error: 'SYS_ICC_IGRPEN0_EL1' undeclared (first use in this function) 1038 | write_sysreg_s(1, SYS_ICC_IGRPEN0_EL1); | ^~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c: In function 'gic_init_bases': 1743 | set_handle_irq_entry(gic_handle_irq, 0); | ^~~~~~~~~~~~~~~~~~~~ | set_handle_irq cc1: some warnings being treated as errors vim +1743 drivers/irqchip/irq-gic-v3.c 1677 1678 static int __init gic_init_bases(void __iomem *dist_base, 1679 struct redist_region *rdist_regs, 1680 u32 nr_redist_regions, 1681 u64 redist_stride, 1682 struct fwnode_handle *handle) 1683 { 1684 u32 typer; 1685 int err; 1686 1687 if (!is_hyp_mode_available()) 1688 static_branch_disable(&supports_deactivate_key); 1689 1690 if (static_branch_likely(&supports_deactivate_key)) 1691 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1692 1693 gic_data.fwnode = handle; 1694 gic_data.dist_base = dist_base; 1695 gic_data.redist_regions = rdist_regs; 1696 gic_data.nr_redist_regions = nr_redist_regions; 1697 gic_data.redist_stride = redist_stride; 1698 1699 /* 1700 * Find out how many interrupts are supported. 1701 */ 1702 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 1703 gic_data.rdists.gicd_typer = typer; 1704 1705 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), 1706 gic_quirks, &gic_data); 1707 1708 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); 1709 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); 1710 1711 /* 1712 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the 1713 * architecture spec (which says that reserved registers are RES0). 1714 */ 1715 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) 1716 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); 1717 1718 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1719 &gic_data); 1720 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1721 gic_data.rdists.has_rvpeid = true; 1722 gic_data.rdists.has_vlpis = true; 1723 gic_data.rdists.has_direct_lpi = true; 1724 gic_data.rdists.has_vpend_valid_dirty = true; 1725 1726 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 1727 err = -ENOMEM; 1728 goto out_free; 1729 } 1730 1731 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1732 1733 gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1734 pr_info("Distributor has %sRange Selector support\n", 1735 gic_data.has_rss ? "" : "no "); 1736 1737 if (typer & GICD_TYPER_MBIS) { 1738 err = mbi_init(handle, gic_data.domain); 1739 if (err) 1740 pr_err("Failed to initialize MBIs\n"); 1741 } 1742 1744 set_handle_irq_entry(gic_handle_fiq, 1); 1745 1746 gic_update_rdist_properties(); 1747 1748 gic_dist_init(); 1749 gic_cpu_init(); 1750 gic_smp_init(); 1751 gic_cpu_pm_init(); 1752 1753 if (gic_dist_supports_lpis()) { 1754 its_init(handle, &gic_data.rdists, gic_data.domain); 1755 its_cpu_init(); 1756 } else { 1757 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1758 gicv2m_init(handle, gic_data.domain); 1759 } 1760 1761 gic_enable_nmi_support(); 1762 1763 return 0; 1764 1765 out_free: 1766 if (gic_data.domain) 1767 irq_domain_remove(gic_data.domain); 1768 free_percpu(gic_data.rdists.rdist); 1769 return err; 1770 } 1771 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org