[kbuild-all] drivers/pci/controller/pci-ixp4xx.c:148:12: error: 'ixp4xx_pci_read' redeclared as different kind of symbol

tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 761c6d7ec820f123b931e7b8ef7ec7c8564e450f commit: 5f291bfd33c8995c69f5a50f21445a4a93584ed2 arm: Typo s/PCI_IXP4XX_LEGACY/IXP4XX_PCI_LEGACY/ date: 4 weeks ago config: arm-randconfig-r032-20210811 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 10.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit... git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 5f291bfd33c8995c69f5a50f21445a4a93584ed2 # save the attached .config to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross O=build_dir ARCH=arm SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/pci/controller/pci-ixp4xx.c:38: warning: "IXP4XX_PCI_CSR" redefined 38 | #define IXP4XX_PCI_CSR 0x1c | In file included from arch/arm/mach-ixp4xx/include/mach/hardware.h:23, from arch/arm/mach-ixp4xx/include/mach/io.h:15, from arch/arm/include/asm/io.h:198, from include/linux/io.h:13, from drivers/pci/controller/pci-ixp4xx.c:20: arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h:221: note: this is the location of the previous definition 221 | #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) | 148 | static int ixp4xx_pci_read(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) | ^~~~~~~~~~~~~~~ In file included from arch/arm/include/asm/io.h:198, from include/linux/io.h:13, from drivers/pci/controller/pci-ixp4xx.c:20: arch/arm/mach-ixp4xx/include/mach/io.h:17:14: note: previous declaration of 'ixp4xx_pci_read' was here 17 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); | ^~~~~~~~~~~~~~~ 173 | static int ixp4xx_pci_write(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) | ^~~~~~~~~~~~~~~~ In file included from arch/arm/include/asm/io.h:198, from include/linux/io.h:13, from drivers/pci/controller/pci-ixp4xx.c:20: arch/arm/mach-ixp4xx/include/mach/io.h:18:12: note: previous declaration of 'ixp4xx_pci_write' was here 18 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | ^~~~~~~~~~~~~~~~ vim +/ixp4xx_pci_read +148 drivers/pci/controller/pci-ixp4xx.c f7821b49345848 Linus Walleij 2021-05-03 @20 #include <linux/io.h> f7821b49345848 Linus Walleij 2021-05-03 21 #include <linux/kernel.h> f7821b49345848 Linus Walleij 2021-05-03 22 #include <linux/of_address.h> f7821b49345848 Linus Walleij 2021-05-03 23 #include <linux/of_device.h> f7821b49345848 Linus Walleij 2021-05-03 24 #include <linux/of_pci.h> f7821b49345848 Linus Walleij 2021-05-03 25 #include <linux/pci.h> f7821b49345848 Linus Walleij 2021-05-03 26 #include <linux/platform_device.h> f7821b49345848 Linus Walleij 2021-05-03 27 #include <linux/slab.h> f7821b49345848 Linus Walleij 2021-05-03 28 #include <linux/bits.h> f7821b49345848 Linus Walleij 2021-05-03 29 f7821b49345848 Linus Walleij 2021-05-03 30 /* Register offsets */ f7821b49345848 Linus Walleij 2021-05-03 31 #define IXP4XX_PCI_NP_AD 0x00 f7821b49345848 Linus Walleij 2021-05-03 32 #define IXP4XX_PCI_NP_CBE 0x04 f7821b49345848 Linus Walleij 2021-05-03 33 #define IXP4XX_PCI_NP_WDATA 0x08 f7821b49345848 Linus Walleij 2021-05-03 34 #define IXP4XX_PCI_NP_RDATA 0x0c f7821b49345848 Linus Walleij 2021-05-03 35 #define IXP4XX_PCI_CRP_AD_CBE 0x10 f7821b49345848 Linus Walleij 2021-05-03 36 #define IXP4XX_PCI_CRP_WDATA 0x14 f7821b49345848 Linus Walleij 2021-05-03 37 #define IXP4XX_PCI_CRP_RDATA 0x18 f7821b49345848 Linus Walleij 2021-05-03 38 #define IXP4XX_PCI_CSR 0x1c f7821b49345848 Linus Walleij 2021-05-03 39 #define IXP4XX_PCI_ISR 0x20 f7821b49345848 Linus Walleij 2021-05-03 40 #define IXP4XX_PCI_INTEN 0x24 f7821b49345848 Linus Walleij 2021-05-03 41 #define IXP4XX_PCI_DMACTRL 0x28 f7821b49345848 Linus Walleij 2021-05-03 42 #define IXP4XX_PCI_AHBMEMBASE 0x2c f7821b49345848 Linus Walleij 2021-05-03 43 #define IXP4XX_PCI_AHBIOBASE 0x30 f7821b49345848 Linus Walleij 2021-05-03 44 #define IXP4XX_PCI_PCIMEMBASE 0x34 f7821b49345848 Linus Walleij 2021-05-03 45 #define IXP4XX_PCI_AHBDOORBELL 0x38 f7821b49345848 Linus Walleij 2021-05-03 46 #define IXP4XX_PCI_PCIDOORBELL 0x3c f7821b49345848 Linus Walleij 2021-05-03 47 #define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 f7821b49345848 Linus Walleij 2021-05-03 48 #define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 f7821b49345848 Linus Walleij 2021-05-03 49 #define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 f7821b49345848 Linus Walleij 2021-05-03 50 #define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c f7821b49345848 Linus Walleij 2021-05-03 51 #define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 f7821b49345848 Linus Walleij 2021-05-03 52 #define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 f7821b49345848 Linus Walleij 2021-05-03 53 f7821b49345848 Linus Walleij 2021-05-03 54 /* CSR bit definitions */ f7821b49345848 Linus Walleij 2021-05-03 55 #define IXP4XX_PCI_CSR_HOST BIT(0) f7821b49345848 Linus Walleij 2021-05-03 56 #define IXP4XX_PCI_CSR_ARBEN BIT(1) f7821b49345848 Linus Walleij 2021-05-03 57 #define IXP4XX_PCI_CSR_ADS BIT(2) f7821b49345848 Linus Walleij 2021-05-03 58 #define IXP4XX_PCI_CSR_PDS BIT(3) f7821b49345848 Linus Walleij 2021-05-03 59 #define IXP4XX_PCI_CSR_ABE BIT(4) f7821b49345848 Linus Walleij 2021-05-03 60 #define IXP4XX_PCI_CSR_DBT BIT(5) f7821b49345848 Linus Walleij 2021-05-03 61 #define IXP4XX_PCI_CSR_ASE BIT(8) f7821b49345848 Linus Walleij 2021-05-03 62 #define IXP4XX_PCI_CSR_IC BIT(15) f7821b49345848 Linus Walleij 2021-05-03 63 #define IXP4XX_PCI_CSR_PRST BIT(16) f7821b49345848 Linus Walleij 2021-05-03 64 f7821b49345848 Linus Walleij 2021-05-03 65 /* ISR (Interrupt status) Register bit definitions */ f7821b49345848 Linus Walleij 2021-05-03 66 #define IXP4XX_PCI_ISR_PSE BIT(0) f7821b49345848 Linus Walleij 2021-05-03 67 #define IXP4XX_PCI_ISR_PFE BIT(1) f7821b49345848 Linus Walleij 2021-05-03 68 #define IXP4XX_PCI_ISR_PPE BIT(2) f7821b49345848 Linus Walleij 2021-05-03 69 #define IXP4XX_PCI_ISR_AHBE BIT(3) f7821b49345848 Linus Walleij 2021-05-03 70 #define IXP4XX_PCI_ISR_APDC BIT(4) f7821b49345848 Linus Walleij 2021-05-03 71 #define IXP4XX_PCI_ISR_PADC BIT(5) f7821b49345848 Linus Walleij 2021-05-03 72 #define IXP4XX_PCI_ISR_ADB BIT(6) f7821b49345848 Linus Walleij 2021-05-03 73 #define IXP4XX_PCI_ISR_PDB BIT(7) f7821b49345848 Linus Walleij 2021-05-03 74 f7821b49345848 Linus Walleij 2021-05-03 75 /* INTEN (Interrupt Enable) Register bit definitions */ f7821b49345848 Linus Walleij 2021-05-03 76 #define IXP4XX_PCI_INTEN_PSE BIT(0) f7821b49345848 Linus Walleij 2021-05-03 77 #define IXP4XX_PCI_INTEN_PFE BIT(1) f7821b49345848 Linus Walleij 2021-05-03 78 #define IXP4XX_PCI_INTEN_PPE BIT(2) f7821b49345848 Linus Walleij 2021-05-03 79 #define IXP4XX_PCI_INTEN_AHBE BIT(3) f7821b49345848 Linus Walleij 2021-05-03 80 #define IXP4XX_PCI_INTEN_APDC BIT(4) f7821b49345848 Linus Walleij 2021-05-03 81 #define IXP4XX_PCI_INTEN_PADC BIT(5) f7821b49345848 Linus Walleij 2021-05-03 82 #define IXP4XX_PCI_INTEN_ADB BIT(6) f7821b49345848 Linus Walleij 2021-05-03 83 #define IXP4XX_PCI_INTEN_PDB BIT(7) f7821b49345848 Linus Walleij 2021-05-03 84 f7821b49345848 Linus Walleij 2021-05-03 85 /* Shift value for byte enable on NP cmd/byte enable register */ f7821b49345848 Linus Walleij 2021-05-03 86 #define IXP4XX_PCI_NP_CBE_BESL 4 f7821b49345848 Linus Walleij 2021-05-03 87 f7821b49345848 Linus Walleij 2021-05-03 88 /* PCI commands supported by NP access unit */ f7821b49345848 Linus Walleij 2021-05-03 89 #define NP_CMD_IOREAD 0x2 f7821b49345848 Linus Walleij 2021-05-03 90 #define NP_CMD_IOWRITE 0x3 f7821b49345848 Linus Walleij 2021-05-03 91 #define NP_CMD_CONFIGREAD 0xa f7821b49345848 Linus Walleij 2021-05-03 92 #define NP_CMD_CONFIGWRITE 0xb f7821b49345848 Linus Walleij 2021-05-03 93 #define NP_CMD_MEMREAD 0x6 f7821b49345848 Linus Walleij 2021-05-03 94 #define NP_CMD_MEMWRITE 0x7 f7821b49345848 Linus Walleij 2021-05-03 95 f7821b49345848 Linus Walleij 2021-05-03 96 /* Constants for CRP access into local config space */ f7821b49345848 Linus Walleij 2021-05-03 97 #define CRP_AD_CBE_BESL 20 f7821b49345848 Linus Walleij 2021-05-03 98 #define CRP_AD_CBE_WRITE 0x00010000 f7821b49345848 Linus Walleij 2021-05-03 99 f7821b49345848 Linus Walleij 2021-05-03 100 /* Special PCI configuration space registers for this controller */ f7821b49345848 Linus Walleij 2021-05-03 101 #define IXP4XX_PCI_RTOTTO 0x40 f7821b49345848 Linus Walleij 2021-05-03 102 f7821b49345848 Linus Walleij 2021-05-03 103 struct ixp4xx_pci { f7821b49345848 Linus Walleij 2021-05-03 104 struct device *dev; f7821b49345848 Linus Walleij 2021-05-03 105 void __iomem *base; f7821b49345848 Linus Walleij 2021-05-03 106 bool errata_hammer; f7821b49345848 Linus Walleij 2021-05-03 107 bool host_mode; f7821b49345848 Linus Walleij 2021-05-03 108 }; f7821b49345848 Linus Walleij 2021-05-03 109 f7821b49345848 Linus Walleij 2021-05-03 110 /* f7821b49345848 Linus Walleij 2021-05-03 111 * The IXP4xx has a peculiar address bus that will change the f7821b49345848 Linus Walleij 2021-05-03 112 * byte order on SoC peripherals depending on whether the device f7821b49345848 Linus Walleij 2021-05-03 113 * operates in big-endian or little-endian mode. That means that f7821b49345848 Linus Walleij 2021-05-03 114 * readl() and writel() that always use little-endian access f7821b49345848 Linus Walleij 2021-05-03 115 * will not work for SoC peripherals such as the PCI controller f7821b49345848 Linus Walleij 2021-05-03 116 * when used in big-endian mode. The accesses to the individual f7821b49345848 Linus Walleij 2021-05-03 117 * PCI devices on the other hand, are always little-endian and f7821b49345848 Linus Walleij 2021-05-03 118 * can use readl() and writel(). f7821b49345848 Linus Walleij 2021-05-03 119 * f7821b49345848 Linus Walleij 2021-05-03 120 * For local AHB bus access we need to use __raw_[readl|writel]() f7821b49345848 Linus Walleij 2021-05-03 121 * to make sure that we access the SoC devices in the CPU native f7821b49345848 Linus Walleij 2021-05-03 122 * endianness. f7821b49345848 Linus Walleij 2021-05-03 123 */ f7821b49345848 Linus Walleij 2021-05-03 124 static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) f7821b49345848 Linus Walleij 2021-05-03 125 { f7821b49345848 Linus Walleij 2021-05-03 126 return __raw_readl(p->base + reg); f7821b49345848 Linus Walleij 2021-05-03 127 } f7821b49345848 Linus Walleij 2021-05-03 128 f7821b49345848 Linus Walleij 2021-05-03 129 static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) f7821b49345848 Linus Walleij 2021-05-03 130 { f7821b49345848 Linus Walleij 2021-05-03 131 __raw_writel(val, p->base + reg); f7821b49345848 Linus Walleij 2021-05-03 132 } f7821b49345848 Linus Walleij 2021-05-03 133 f7821b49345848 Linus Walleij 2021-05-03 134 static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) f7821b49345848 Linus Walleij 2021-05-03 135 { f7821b49345848 Linus Walleij 2021-05-03 136 u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); f7821b49345848 Linus Walleij 2021-05-03 137 f7821b49345848 Linus Walleij 2021-05-03 138 if (isr & IXP4XX_PCI_ISR_PFE) { f7821b49345848 Linus Walleij 2021-05-03 139 /* Make sure the master abort bit is reset */ f7821b49345848 Linus Walleij 2021-05-03 140 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); f7821b49345848 Linus Walleij 2021-05-03 141 dev_dbg(p->dev, "master abort detected\n"); f7821b49345848 Linus Walleij 2021-05-03 142 return -EINVAL; f7821b49345848 Linus Walleij 2021-05-03 143 } f7821b49345848 Linus Walleij 2021-05-03 144 f7821b49345848 Linus Walleij 2021-05-03 145 return 0; f7821b49345848 Linus Walleij 2021-05-03 146 } f7821b49345848 Linus Walleij 2021-05-03 147 f7821b49345848 Linus Walleij 2021-05-03 @148 static int ixp4xx_pci_read(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) f7821b49345848 Linus Walleij 2021-05-03 149 { f7821b49345848 Linus Walleij 2021-05-03 150 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); f7821b49345848 Linus Walleij 2021-05-03 151 f7821b49345848 Linus Walleij 2021-05-03 152 if (p->errata_hammer) { f7821b49345848 Linus Walleij 2021-05-03 153 int i; f7821b49345848 Linus Walleij 2021-05-03 154 f7821b49345848 Linus Walleij 2021-05-03 155 /* f7821b49345848 Linus Walleij 2021-05-03 156 * PCI workaround - only works if NP PCI space reads have f7821b49345848 Linus Walleij 2021-05-03 157 * no side effects. Hammer the register and read twice 8 f7821b49345848 Linus Walleij 2021-05-03 158 * times. last one will be good. f7821b49345848 Linus Walleij 2021-05-03 159 */ f7821b49345848 Linus Walleij 2021-05-03 160 for (i = 0; i < 8; i++) { f7821b49345848 Linus Walleij 2021-05-03 161 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); f7821b49345848 Linus Walleij 2021-05-03 162 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); f7821b49345848 Linus Walleij 2021-05-03 163 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); f7821b49345848 Linus Walleij 2021-05-03 164 } f7821b49345848 Linus Walleij 2021-05-03 165 } else { f7821b49345848 Linus Walleij 2021-05-03 166 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); f7821b49345848 Linus Walleij 2021-05-03 167 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); f7821b49345848 Linus Walleij 2021-05-03 168 } f7821b49345848 Linus Walleij 2021-05-03 169 f7821b49345848 Linus Walleij 2021-05-03 170 return ixp4xx_pci_check_master_abort(p); f7821b49345848 Linus Walleij 2021-05-03 171 } f7821b49345848 Linus Walleij 2021-05-03 172 f7821b49345848 Linus Walleij 2021-05-03 @173 static int ixp4xx_pci_write(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) f7821b49345848 Linus Walleij 2021-05-03 174 { f7821b49345848 Linus Walleij 2021-05-03 175 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); f7821b49345848 Linus Walleij 2021-05-03 176 f7821b49345848 Linus Walleij 2021-05-03 177 /* Set up the write */ f7821b49345848 Linus Walleij 2021-05-03 178 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); f7821b49345848 Linus Walleij 2021-05-03 179 f7821b49345848 Linus Walleij 2021-05-03 180 /* Execute the write by writing to NP_WDATA */ f7821b49345848 Linus Walleij 2021-05-03 181 ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); f7821b49345848 Linus Walleij 2021-05-03 182 f7821b49345848 Linus Walleij 2021-05-03 183 return ixp4xx_pci_check_master_abort(p); f7821b49345848 Linus Walleij 2021-05-03 184 } f7821b49345848 Linus Walleij 2021-05-03 185 :::::: The code at line 148 was first introduced by commit :::::: f7821b49345848246692c6e0aa170c8bc6723f86 PCI: ixp4xx: Add a new driver for IXP4xx :::::: TO: Linus Walleij <linus.walleij(a)linaro.org&gt; :::::: CC: Linus Walleij <linus.walleij(a)linaro.org&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org