3:29 p.m.
Hi Ben,
I love your patch! Perhaps something to improve:
[auto build test WARNING on 53989fad1286e652ea3655ae3367ba698da8d2ff]
url:
https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL...
base: 53989fad1286e652ea3655ae3367ba698da8d2ff
config: riscv-buildonly-randconfig-r001-20211119 (attached as .config)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
#
https://github.com/0day-ci/linux/commit/cfdf51e15fc8229a494ee59d05bc7459a...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
git checkout cfdf51e15fc8229a494ee59d05bc7459ab5eecd8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
> drivers/cxl/pci.c:469:7: warning: variable 'size' set but
not used [-Wunused-but-set-variable]
u64 size;
^
1 warning generated.
vim +/size +469 drivers/cxl/pci.c
454
455 #define CDPD(cxlds, which) \
456 cxlds->device_dvsec + CXL_DVSEC_PCIE_DEVICE_##which##_OFFSET
457
458 #define CDPDR(cxlds, which, sorb, lohi) \
459 cxlds->device_dvsec + \
460 CXL_DVSEC_PCIE_DEVICE_RANGE_##sorb##_##lohi##_OFFSET(which)
461
462 static int wait_for_valid(struct cxl_dev_state *cxlds)
463 {
464 struct pci_dev *pdev = to_pci_dev(cxlds->dev);
465 const unsigned long timeout = jiffies + HZ;
466 bool valid;
467
468 do {
469 u64 size;
470 u32 temp;
471 int rc;
472
473 rc = pci_read_config_dword(pdev, CDPDR(cxlds, 0, SIZE, HIGH),
474 &temp);
475 if (rc)
476 return -ENXIO;
477 size = (u64)temp << 32;
478
479 rc = pci_read_config_dword(pdev, CDPDR(cxlds, 0, SIZE, LOW),
480 &temp);
481 if (rc)
482 return -ENXIO;
483 size |= temp & CXL_DVSEC_PCIE_DEVICE_MEM_SIZE_LOW_MASK;
484
485 /*
486 * Memory_Info_Valid: When set, indicates that the CXL Range 1
487 * Size high and Size Low registers are valid. Must be set
488 * within 1 second of deassertion of reset to CXL device.
489 */
490 valid = FIELD_GET(CXL_DVSEC_PCIE_DEVICE_MEM_INFO_VALID, temp);
491 if (valid)
492 break;
493 cpu_relax();
494 } while (!time_after(jiffies, timeout));
495
496 return valid ? 0 : -ETIMEDOUT;
497 }
498
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org