[kbuild-all] Re: [PATCH v6 3/3] mtd: rawnand: Add support for secure regions in NAND memory

Hi Manivannan, I love your patch! Perhaps something to improve: [auto build test WARNING on mtd/mtd/next] [also build test WARNING on mtd/mtd/fixes mtd/nand/next v5.12-rc3 next-20210318] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Manivannan-Sadhasivam/Add-suppor... base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/next config: arm-randconfig-r023-20210318 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 6db3ab2903f42712f44000afb5aa467efbd25f35) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/0day-ci/linux/commit/045edb4991f99260412ca8ecbcbf1f41f... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Manivannan-Sadhasivam/Add-support-for-secure-regions-in-NAND/20210318-204636 git checkout 045edb4991f99260412ca8ecbcbf1f41fcd30941 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): ret = nand_check_secure_region(chip, instr->addr, len); ^~~ drivers/mtd/nand/raw/nand_base.c:4245:12: note: initialize the variable 'len' to silence this warning loff_t len; ^ = 0 1 warning generated. vim +/len +4255 drivers/mtd/nand/raw/nand_base.c 4232 4233 /** 4234 * nand_erase_nand - [INTERN] erase block(s) 4235 * @chip: NAND chip object 4236 * @instr: erase instruction 4237 * @allowbbt: allow erasing the bbt area 4238 * 4239 * Erase one ore more blocks. 4240 */ 4241 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, 4242 int allowbbt) 4243 { 4244 int page, pages_per_block, ret, chipnr; 4245 loff_t len; 4246 4247 pr_debug("%s: start = 0x%012llx, len = %llu\n", 4248 __func__, (unsigned long long)instr->addr, 4249 (unsigned long long)instr->len); 4250 4251 if (check_offs_len(chip, instr->addr, instr->len)) 4252 return -EINVAL; 4253 4254 /* Check if the region is secured */ 4256 if (ret) 4257 return ret; 4258 4259 /* Grab the lock and see if the device is available */ 4260 ret = nand_get_device(chip); 4261 if (ret) 4262 return ret; 4263 4264 /* Shift to get first page */ 4265 page = (int)(instr->addr >> chip->page_shift); 4266 chipnr = (int)(instr->addr >> chip->chip_shift); 4267 4268 /* Calculate pages in each block */ 4269 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 4270 4271 /* Select the NAND device */ 4272 nand_select_target(chip, chipnr); 4273 4274 /* Check, if it is write protected */ 4275 if (nand_check_wp(chip)) { 4276 pr_debug("%s: device is write protected!\n", 4277 __func__); 4278 ret = -EIO; 4279 goto erase_exit; 4280 } 4281 4282 /* Loop through the pages */ 4283 len = instr->len; 4284 4285 while (len) { 4286 /* Check if we have a bad block, we do not erase bad blocks! */ 4287 if (nand_block_checkbad(chip, ((loff_t) page) << 4288 chip->page_shift, allowbbt)) { 4289 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", 4290 __func__, page); 4291 ret = -EIO; 4292 goto erase_exit; 4293 } 4294 4295 /* 4296 * Invalidate the page cache, if we erase the block which 4297 * contains the current cached page. 4298 */ 4299 if (page <= chip->pagecache.page && chip->pagecache.page < 4300 (page + pages_per_block)) 4301 chip->pagecache.page = -1; 4302 4303 ret = nand_erase_op(chip, (page & chip->pagemask) >> 4304 (chip->phys_erase_shift - chip->page_shift)); 4305 if (ret) { 4306 pr_debug("%s: failed erase, page 0x%08x\n", 4307 __func__, page); 4308 instr->fail_addr = 4309 ((loff_t)page << chip->page_shift); 4310 goto erase_exit; 4311 } 4312 4313 /* Increment page address and decrement length */ 4314 len -= (1ULL << chip->phys_erase_shift); 4315 page += pages_per_block; 4316 4317 /* Check, if we cross a chip boundary */ 4318 if (len && !(page & chip->pagemask)) { 4319 chipnr++; 4320 nand_deselect_target(chip); 4321 nand_select_target(chip, chipnr); 4322 } 4323 } 4324 4325 ret = 0; 4326 erase_exit: 4327 4328 /* Deselect and wake up anyone waiting on the device */ 4329 nand_deselect_target(chip); 4330 nand_release_device(chip); 4331 4332 /* Return more or less happy */ 4333 return ret; 4334 } 4335 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org