1:29 a.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/andrea/aa.git master
head: ba6dcb432380cad8961d1e7297b2e080edb1782d
commit: a99fedbd322ac64c3707e5e05f2a3cc75fbefc88 [40/42] arm64: tlb: skip tlbi broadcast
config: arm64-randconfig-r012-20210209 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
#
https://git.kernel.org/pub/scm/linux/kernel/git/andrea/aa.git/commit/?id=...
git remote add aa https://git.kernel.org/pub/scm/linux/kernel/git/andrea/aa.git
git fetch --no-tags aa master
git checkout a99fedbd322ac64c3707e5e05f2a3cc75fbefc88
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
> arch/arm64/mm/context.c:248:6: warning: variable 'cpu' is
used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
if (old_active_asid && asid_gen_match(asid) &&
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/mm/context.c:274:23: note: uninitialized use occurs here
if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
^~~
arch/arm64/mm/context.c:248:2: note: remove the 'if' if its condition is always
false
if (old_active_asid && asid_gen_match(asid) &&
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/mm/context.c:225:18: note: initialize the variable 'cpu' to silence
this warning
unsigned int cpu;
^
= 0
1 warning generated.
vim +248 arch/arm64/mm/context.c
b3901d54dc4f73 Catalin Marinas 2012-03-05 221
c4885bbb3afee8 Pingfan Liu 2020-07-10 222 void check_and_switch_context(struct
mm_struct *mm)
b3901d54dc4f73 Catalin Marinas 2012-03-05 223 {
5aec715d7d3122 Will Deacon 2015-10-06 224 unsigned long flags;
c4885bbb3afee8 Pingfan Liu 2020-07-10 225 unsigned int cpu;
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 226 u64 asid, old_active_asid;
5aec715d7d3122 Will Deacon 2015-10-06 227
5ffdfaedfa0aba Vladimir Murzin 2018-07-31 228 if (system_supports_cnp())
5ffdfaedfa0aba Vladimir Murzin 2018-07-31 229 cpu_set_reserved_ttbr0();
5ffdfaedfa0aba Vladimir Murzin 2018-07-31 230
5aec715d7d3122 Will Deacon 2015-10-06 231 asid =
atomic64_read(&mm->context.id);
b3901d54dc4f73 Catalin Marinas 2012-03-05 232
b3901d54dc4f73 Catalin Marinas 2012-03-05 233 /*
3a33c7605750fb Will Deacon 2017-11-30 234 * The memory ordering here is
subtle.
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 235 * If our active_asids is non-zero
and the ASID matches the current
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 236 * generation, then we update the
active_asids entry with a relaxed
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 237 * cmpxchg. Racing with a
concurrent rollover means that either:
3a33c7605750fb Will Deacon 2017-11-30 238 *
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 239 * - We get a zero back from the
cmpxchg and end up waiting on the
3a33c7605750fb Will Deacon 2017-11-30 240 * lock. Taking the lock
synchronises with the rollover and so
3a33c7605750fb Will Deacon 2017-11-30 241 * we are forced to see the
updated generation.
3a33c7605750fb Will Deacon 2017-11-30 242 *
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 243 * - We get a valid ASID back from
the cmpxchg, which means the
3a33c7605750fb Will Deacon 2017-11-30 244 * relaxed xchg in flush_context
will treat us as reserved
3a33c7605750fb Will Deacon 2017-11-30 245 * because atomic RmWs are
totally ordered for a given location.
b3901d54dc4f73 Catalin Marinas 2012-03-05 246 */
c4885bbb3afee8 Pingfan Liu 2020-07-10 247 old_active_asid =
atomic64_read(this_cpu_ptr(&active_asids));
4fc92254bf86b1 Jean-Philippe Brucker 2020-05-19 @248 if (old_active_asid &&
asid_gen_match(asid) &&
c4885bbb3afee8 Pingfan Liu 2020-07-10 249
atomic64_cmpxchg_relaxed(this_cpu_ptr(&active_asids),
a8ffaaa060b8d4 Catalin Marinas 2017-12-27 250 old_active_asid, asid))
5aec715d7d3122 Will Deacon 2015-10-06 251 goto switch_mm_fastpath;
5aec715d7d3122 Will Deacon 2015-10-06 252
5aec715d7d3122 Will Deacon 2015-10-06 253
raw_spin_lock_irqsave(&cpu_asid_lock, flags);
5aec715d7d3122 Will Deacon 2015-10-06 254 /* Check that our ASID belongs to
the current generation. */
5aec715d7d3122 Will Deacon 2015-10-06 255 asid =
atomic64_read(&mm->context.id);
4fc92254bf86b1 Jean-Philippe Brucker 2020-05-19 256 if (!asid_gen_match(asid)) {
742fafa50b62cb Shaokun Zhang 2018-10-06 257 asid = new_context(mm);
5aec715d7d3122 Will Deacon 2015-10-06 258
atomic64_set(&mm->context.id, asid);
b3901d54dc4f73 Catalin Marinas 2012-03-05 259 }
b3901d54dc4f73 Catalin Marinas 2012-03-05 260
c4885bbb3afee8 Pingfan Liu 2020-07-10 261 cpu = smp_processor_id();
5aec715d7d3122 Will Deacon 2015-10-06 262 if (cpumask_test_and_clear_cpu(cpu,
&tlb_flush_pending))
5aec715d7d3122 Will Deacon 2015-10-06 263 local_flush_tlb_all();
5aec715d7d3122 Will Deacon 2015-10-06 264
c4885bbb3afee8 Pingfan Liu 2020-07-10 265
atomic64_set(this_cpu_ptr(&active_asids), asid);
5aec715d7d3122 Will Deacon 2015-10-06 266
raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
5aec715d7d3122 Will Deacon 2015-10-06 267
5aec715d7d3122 Will Deacon 2015-10-06 268 switch_mm_fastpath:
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 269 /*
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 270 * Enforce CPU ordering between the
atomic_inc(nr_active_mm)
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 271 * in switch_mm() and the below
cpumask_test_cpu(mm_cpumask).
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 272 */
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 273 smp_mb();
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 274 if (cpumask_test_cpu(cpu,
mm_cpumask(mm))) {
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 275 cpumask_clear_cpu(cpu,
mm_cpumask(mm));
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 276 local_flush_tlb_asid(asid);
a99fedbd322ac6 Andrea Arcangeli 2019-12-03 277 }
a8e4c0a919ae31 Marc Zyngier 2018-01-19 278
a8e4c0a919ae31 Marc Zyngier 2018-01-19 279 arm64_apply_bp_hardening();
a8e4c0a919ae31 Marc Zyngier 2018-01-19 280
39bc88e5e38e9b Catalin Marinas 2016-09-02 281 /*
39bc88e5e38e9b Catalin Marinas 2016-09-02 282 * Defer TTBR0_EL1 setting for user
threads to uaccess_enable() when
39bc88e5e38e9b Catalin Marinas 2016-09-02 283 * emulating PAN.
39bc88e5e38e9b Catalin Marinas 2016-09-02 284 */
39bc88e5e38e9b Catalin Marinas 2016-09-02 285 if (!system_uses_ttbr0_pan())
5aec715d7d3122 Will Deacon 2015-10-06 286 cpu_switch_mm(mm->pgd, mm);
5aec715d7d3122 Will Deacon 2015-10-06 287 }
5aec715d7d3122 Will Deacon 2015-10-06 288
:::::: The code at line 248 was first introduced by commit
:::::: 4fc92254bf86b19ac1ef81f61f4e690fccfcba4a arm64: mm: Add asid_gen_match() helper
:::::: TO: Jean-Philippe Brucker <jean-philippe(a)linaro.org>
:::::: CC: Will Deacon <will(a)kernel.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org