[kbuild-all] [agd5f:drm-next 393/414] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_init.c:30:6: warning: no previous prototype for function 'dcn303_hw_sequencer_construct'

tree: https://gitlab.freedesktop.org/agd5f/linux.git drm-next head: 2117d5f920190bd219e1aca5bf903477781ca161 commit: 774f62c5206248846cafa1513a4c6a05f0f5e06c [393/414] drm/amd/display: Initial DC support for Beige Goby config: x86_64-randconfig-a003-20210517 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project ceb1ac9812cb0972cfa34cecc5e5704ae2a22063) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu git remote add agd5f https://gitlab.freedesktop.org/agd5f/linux.git git fetch --no-tags agd5f drm-next git checkout 774f62c5206248846cafa1513a4c6a05f0f5e06c # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): void dcn303_hw_sequencer_construct(struct dc *dc) ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_init.c:30:1: note: declare 'static' if the function is not intended to be used outside of this translation unit void dcn303_hw_sequencer_construct(struct dc *dc) ^ static 1 warning generated. -- stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:106:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:148:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:499:3: note: previous initialization is here stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:101:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:98:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:107:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:158:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:499:3: note: previous initialization is here stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:102:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:108:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:108:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DIG_FE_CNTL, DIG, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:168:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:499:3: note: previous initialization is here stream_enc_regs(0), ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:50:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DIG_FE_CNTL, DIG, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:43:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:500:3: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides] stream_enc_regs(1) ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:106:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:248:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:500:3: note: previous initialization is here stream_enc_regs(1) ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:101:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:304:25: note: expanded from macro 'BASE_INNER' #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ^ <scratch space>:198:1: note: expanded from here DCN_BASE__INST0_SEG2 ^ drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:372:52: note: expanded from macro 'DCN_BASE__INST0_SEG2' #define DCN_BASE__INST0_SEG2 0x000034C0 ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:500:3: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides] stream_enc_regs(1) ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:496:12: note: expanded from macro 'stream_enc_regs' [id] = { SE_DCN3_REG_LIST(id) } ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:107:2: note: expanded from macro 'SE_DCN3_REG_LIST' SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:315:15: note: expanded from macro 'SRI' .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) vim +/dcn303_hw_sequencer_construct +30 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_init.c 29 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org