[kbuild-all] [habanaai:habanalabs-next 32/38] drivers/misc/habanalabs/gaudi/gaudi.c:3145:6: warning: variable 'val' set but not used

tree: https://github.com/HabanaAI/linux.git habanalabs-next head: 20ae9a7e300f7c35ba07cdfc6eff7e87a56f1b78 commit: 5a8ba1e332c98857b7a6190bf07e60ec48f00c9e [32/38] habanalabs: add gaudi asic-dependent code config: x86_64-allmodconfig (attached as .config) reproduce: # apt-get install sparse # sparse version: v0.6.1-193-gb8fad4bc-dirty git checkout 5a8ba1e332c98857b7a6190bf07e60ec48f00c9e # save the attached .config to linux build tree make C=1 ARCH=x86_64 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_pre_hw_init': u32 val; ^~~ drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_hw_init': drivers/misc/habanalabs/gaudi/gaudi.c:3212:6: warning: variable 'val' set but not used [-Wunused-but-set-variable] u32 val; ^~~ drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_debugfs_read32': } else if ((addr >= DRAM_PHYS_BASE) && ^~ drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_debugfs_write32': drivers/misc/habanalabs/gaudi/gaudi.c:4804:19: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] } else if ((addr >= DRAM_PHYS_BASE) && ^~ drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_debugfs_read64': drivers/misc/habanalabs/gaudi/gaudi.c:4850:19: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] } else if ((addr >= DRAM_PHYS_BASE) && ^~ drivers/misc/habanalabs/gaudi/gaudi.c: In function 'gaudi_debugfs_write64': drivers/misc/habanalabs/gaudi/gaudi.c:4896:19: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] } else if ((addr >= DRAM_PHYS_BASE) && ^~ vim +/val +3145 drivers/misc/habanalabs/gaudi/gaudi.c 3142 3143 static void gaudi_pre_hw_init(struct hl_device *hdev) 3144 { 3146 3147 /* Perform read from the device to make sure device is up */ 3148 val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 3149 3150 /* 3151 * Let's mark in the H/W that we have reached this point. We check 3152 * this value in the reset_before_init function to understand whether 3153 * we need to reset the chip before doing H/W init. This register is 3154 * cleared by the H/W upon H/W reset 3155 */ 3156 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); 3157 3158 /* Set the access through PCI bars (Linux driver only) as secured */ 3159 WREG32(mmPCIE_WRAP_LBW_PROT_OVR, (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK | 3160 PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK)); 3161 3162 /* Perform read to flush the waiting writes to ensure configuration 3163 * was set in the device 3164 */ 3165 val = RREG32(mmPCIE_WRAP_LBW_PROT_OVR); 3166 3167 if (hdev->axi_drain) { 3168 WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, 3169 1 << PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT); 3170 WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, 3171 1 << PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT); 3172 3173 /* Perform read to flush the DRAIN cfg */ 3174 val = RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); 3175 } else { 3176 WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, 0); 3177 WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, 0); 3178 3179 /* Perform read to flush the DRAIN cfg */ 3180 val = RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); 3181 } 3182 3183 /* Configure the reset registers. Must be done as early as possible 3184 * in case we fail during H/W initialization 3185 */ 3186 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H, 3187 (CFG_RST_H_DMA_MASK | 3188 CFG_RST_H_MME_MASK | 3189 CFG_RST_H_SM_MASK | 3190 CFG_RST_H_TPC_MASK)); 3191 3192 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK); 3193 3194 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H, 3195 (CFG_RST_H_HBM_MASK | 3196 CFG_RST_H_TPC_MASK | 3197 CFG_RST_H_NIC_MASK | 3198 CFG_RST_H_SM_MASK | 3199 CFG_RST_H_DMA_MASK | 3200 CFG_RST_H_MME_MASK | 3201 CFG_RST_H_CPU_MASK | 3202 CFG_RST_H_MMU_MASK)); 3203 3204 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L, 3205 (CFG_RST_L_IF_MASK | 3206 CFG_RST_L_PSOC_MASK | 3207 CFG_RST_L_TPC_MASK)); 3208 } 3209 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org