5:41 p.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git queue-5.4
head: b4001462a35a736ae9775784796ae0be700db254
commit: e303fb358e55829f315ac501b46d63808f2fa9d4 [171/194] MIPS: CPU_LOONGSON2EF need
software to maintain cache consistency
config: mips-allyesconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout e303fb358e55829f315ac501b46d63808f2fa9d4
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
arch/mips/mm/dma-noncoherent.c: In function 'cpu_needs_post_dma_flush':
> arch/mips/mm/dma-noncoherent.c:36:7: error:
'CPU_LOONGSON2EF' undeclared (first use in this function); did you mean
'CPU_LOONGSON2'?
36 | case CPU_LOONGSON2EF:
| ^~~~~~~~~~~~~~~
| CPU_LOONGSON2
arch/mips/mm/dma-noncoherent.c:36:7: note: each undeclared identifier is reported only
once for each function it appears in
vim +36 arch/mips/mm/dma-noncoherent.c
16
17 /*
18 * The affected CPUs below in 'cpu_needs_post_dma_flush()' can
speculatively
19 * fill random cachelines with stale data at any time, requiring an extra
20 * flush post-DMA.
21 *
22 * Warning on the terminology - Linux calls an uncached area coherent; MIPS
23 * terminology calls memory areas with hardware maintained coherency coherent.
24 *
25 * Note that the R14000 and R16000 should also be checked for in this condition.
26 * However this function is only called on non-I/O-coherent systems and only the
27 * R10000 and R12000 are used in such systems, the SGI IP28 Indigo² rsp.
28 * SGI IP32 aka O2.
29 */
30 static inline bool cpu_needs_post_dma_flush(struct device *dev)
31 {
32 switch (boot_cpu_type()) {
33 case CPU_R10000:
34 case CPU_R12000:
35 case CPU_BMIPS5000:
36 case CPU_LOONGSON2EF:
37 return true;
38 default:
39 /*
40 * Presence of MAARs suggests that the CPU supports
41 * speculatively prefetching data, and therefore requires
42 * the post-DMA flush/invalidate.
43 */
44 return cpu_has_maar;
45 }
46 }
47
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org