[kbuild-all] [mark-rutland:hacks/fiq 34/35] drivers/irqchip/irq-gic-v3.c:534:3: error: implicit declaration of function 'write_sysreg_s'; did you mean

tree: https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git hacks/fiq head: 7ecf26e12a51f06badbab4da4c3257779414c026 commit: 7fe8b45fa364a813f852e4374892652af346ff1e [34/35] [DO NOT MERGE] irqchip/gic-v3: Route SGI/PPI as FIQ config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?id... git remote add mark-rutland https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git git fetch --no-tags mark-rutland hacks/fiq git checkout 7fe8b45fa364a813f852e4374892652af346ff1e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/irqchip/irq-gic-v3.c: In function 'gic_eoi_irq': 534 | write_sysreg_s(d->hwirq, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~ | write_sysreg 534 | write_sysreg_s(d->hwirq, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c:534:28: note: each undeclared identifier is reported only once for each function it appears in drivers/irqchip/irq-gic-v3.c: In function 'gic_handle_fiq': 686 | irqnr = read_sysreg_s(SYS_ICC_IAR0_EL1); | ^~~~~~~~~~~~~ | read_sysreg 686 | irqnr = read_sysreg_s(SYS_ICC_IAR0_EL1); | ^~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c:704:25: error: 'SYS_ICC_EOIR0_EL1' undeclared (first use in this function) 704 | write_sysreg_s(irqnr, SYS_ICC_EOIR0_EL1); | ^~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c: In function 'gic_cpu_sys_reg_init': 990 | write_sysreg_s(0, SYS_ICC_BPR0_EL1); | ^~~~~~~~~~~~~~~~ | read_ICC_AP1R0_EL1 1038 | write_sysreg_s(1, SYS_ICC_IGRPEN0_EL1); | ^~~~~~~~~~~~~~~~~~~ drivers/irqchip/irq-gic-v3.c: In function 'gic_init_bases': drivers/irqchip/irq-gic-v3.c:1743:2: error: implicit declaration of function 'set_handle_irq_entry'; did you mean 'set_handle_irq'? [-Werror=implicit-function-declaration] 1743 | set_handle_irq_entry(gic_handle_irq, 0); | ^~~~~~~~~~~~~~~~~~~~ | set_handle_irq cc1: some warnings being treated as errors vim +534 drivers/irqchip/irq-gic-v3.c 530 531 static void gic_eoi_irq(struct irq_data *d) 532 { 533 if (d->hwirq < 32) { 535 isb(); 536 return; 537 } 538 gic_write_eoir(gic_irq(d)); 539 } 540 541 static void gic_eoimode1_eoi_irq(struct irq_data *d) 542 { 543 /* 544 * No need to deactivate an LPI, or an interrupt that 545 * is is getting forwarded to a vcpu. 546 */ 547 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 548 return; 549 gic_write_dir(gic_irq(d)); 550 } 551 552 static int gic_set_type(struct irq_data *d, unsigned int type) 553 { 554 enum gic_intid_range range; 555 unsigned int irq = gic_irq(d); 556 void (*rwp_wait)(void); 557 void __iomem *base; 558 u32 offset, index; 559 int ret; 560 561 range = get_intid_range(d); 562 563 /* Interrupt configuration for SGIs can't be changed */ 564 if (range == SGI_RANGE) 565 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 566 567 /* SPIs have restrictions on the supported types */ 568 if ((range == SPI_RANGE || range == ESPI_RANGE) && 569 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 570 return -EINVAL; 571 572 if (gic_irq_in_rdist(d)) { 573 base = gic_data_rdist_sgi_base(); 574 rwp_wait = gic_redist_wait_for_rwp; 575 } else { 576 base = gic_data.dist_base; 577 rwp_wait = gic_dist_wait_for_rwp; 578 } 579 580 offset = convert_offset_index(d, GICD_ICFGR, &index); 581 582 ret = gic_configure_irq(index, type, base + offset, rwp_wait); 583 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 584 /* Misconfigured PPIs are usually not fatal */ 585 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); 586 ret = 0; 587 } 588 589 return ret; 590 } 591 592 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 593 { 594 if (get_intid_range(d) == SGI_RANGE) 595 return -EINVAL; 596 597 if (vcpu) 598 irqd_set_forwarded_to_vcpu(d); 599 else 600 irqd_clr_forwarded_to_vcpu(d); 601 return 0; 602 } 603 604 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 605 { 606 u64 aff; 607 608 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 609 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 610 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 611 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 612 613 return aff; 614 } 615 616 static void gic_deactivate_unhandled(u32 irqnr) 617 { 618 if (static_branch_likely(&supports_deactivate_key)) { 619 if (irqnr < 8192) 620 gic_write_dir(irqnr); 621 } else { 622 gic_write_eoir(irqnr); 623 } 624 } 625 626 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) 627 { 628 bool irqs_enabled = interrupts_enabled(regs); 629 int err; 630 631 if (irqs_enabled) 632 nmi_enter(); 633 634 if (static_branch_likely(&supports_deactivate_key)) 635 gic_write_eoir(irqnr); 636 /* 637 * Leave the PSR.I bit set to prevent other NMIs to be 638 * received while handling this one. 639 * PSR.I will be restored when we ERET to the 640 * interrupted context. 641 */ 642 err = handle_domain_nmi(gic_data.domain, irqnr, regs); 643 if (err) 644 gic_deactivate_unhandled(irqnr); 645 646 if (irqs_enabled) 647 nmi_exit(); 648 } 649 650 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 651 { 652 u32 irqnr; 653 654 irqnr = gic_read_iar(); 655 656 if (gic_supports_nmi() && 657 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 658 gic_handle_nmi(irqnr, regs); 659 return; 660 } 661 662 if (gic_prio_masking_enabled()) { 663 gic_pmr_mask_irqs(); 664 gic_arch_enable_irqs(); 665 } 666 667 /* Check for special IDs first */ 668 if ((irqnr >= 1020 && irqnr <= 1023)) 669 return; 670 671 if (static_branch_likely(&supports_deactivate_key)) 672 gic_write_eoir(irqnr); 673 else 674 isb(); 675 676 if (handle_domain_irq(gic_data.domain, irqnr, regs)) { 677 WARN_ONCE(true, "Unexpected interrupt received!\n"); 678 gic_deactivate_unhandled(irqnr); 679 } 680 } 681 682 static asmlinkage void __exception_irq_entry gic_handle_fiq(struct pt_regs *regs) 683 { 684 u32 irqnr; 685 687 688 if (gic_supports_nmi() && 689 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { 690 gic_handle_nmi(irqnr, regs); 691 return; 692 } 693 694 if (gic_prio_masking_enabled()) { 695 gic_pmr_mask_irqs(); 696 gic_arch_enable_irqs(); 697 } 698 699 /* Check for special IDs first */ 700 if ((irqnr >= 1020 && irqnr <= 1023)) 701 return; 702 703 if (static_branch_likely(&supports_deactivate_key)) { 705 } 706 707 isb(); 708 709 if (handle_domain_irq(gic_data.domain, irqnr, regs)) { 710 WARN_ONCE(true, "Unexpected interrupt received!\n"); 711 gic_deactivate_unhandled(irqnr); 712 } 713 } 714 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org