2:19 p.m.
Hi Matt,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next v5.14-rc2 next-20210723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Matt-Roper/Begin-enabling-Xe_HP-...
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-r036-20210723 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project
9625ca5b602616b2f5584e8a49ba93c52c141e40)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/a68b2ebea61d2fe5e32ee5bbc975bc0ed...
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Matt-Roper/Begin-enabling-Xe_HP-SDV-and-DG2-platforms/20210724-014624
git checkout a68b2ebea61d2fe5e32ee5bbc975bc0ed5f507de
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
> drivers/gpu/drm/i915/display/intel_snps_phy.c:29:8: error:
implicit declaration of function 'intel_phy_is_snps'
[-Werror,-Wimplicit-function-declaration]
if
(!intel_phy_is_snps(dev_priv, phy))
^
drivers/gpu/drm/i915/display/intel_snps_phy.c:29:8: note: did you mean
'intel_phy_is_tc'?
drivers/gpu/drm/i915/display/intel_display.h:563:6: note: 'intel_phy_is_tc'
declared here
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
^
1 error generated.
vim +/intel_phy_is_snps +29 drivers/gpu/drm/i915/display/intel_snps_phy.c
11
12 /**
13 * DOC: Synopsis PHY support
14 *
15 * Synopsis PHYs are primarily programmed by looking up magic register values
16 * in tables rather than calculating the necessary values at runtime.
17 *
18 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
19 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on
other
20 * platforms and must be programming directly during the modeset sequence
21 * since it is not handled by the shared DPLL framework as on other platforms.
22 */
23
24 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
25 {
26 enum phy phy;
27
28 for_each_phy_masked(phy, ~0) {
29 if (!intel_phy_is_snps(dev_priv, phy))
30 continue;
31
32 if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
33 DG2_PHY_DP_TX_ACK_MASK, 25))
34 DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
35 phy);
36 }
37 }
38
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org