11:27 p.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
watchdog-next
head: 5c9a4cc5516e30ac2e0586e315e0806ae766321b
commit: 10748806ee44ad974d7ccd84c682222213b53e69 [11/23] watchdog: s3c2410: Cleanup PMU
related code
config: arc-randconfig-r015-20211117
(https://download.01.org/0day-ci/archive/20211123/202111232037.iwzPIkeS-lk...)
compiler: arc-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git/...
git remote add groeck-staging
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
git fetch --no-tags groeck-staging watchdog-next
git checkout 10748806ee44ad974d7ccd84c682222213b53e69
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir
ARCH=arc SHELL=/bin/bash drivers/watchdog/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All warnings (new ones prefixed by >>):
> drivers/watchdog/s3c2410_wdt.c:94: warning: expecting prototype
for Quirk flags for different Samsung watchdog IP(). Prototype was for
QUIRK_HAS_WTCLRINT_REG() instead
vim +94 drivers/watchdog/s3c2410_wdt.c
59
60 /**
61 * Quirk flags for different Samsung watchdog IP-cores.
62 *
63 * This driver supports multiple Samsung SoCs, each of which might have
64 * different set of registers and features supported. As watchdog block
65 * sometimes requires modifying PMU registers for proper functioning, register
66 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
67 * flags described below serve the purpose of telling the driver about mentioned
68 * SoC traits, and can be specified in driver data for each particular supported
69 * device.
70 *
71 * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to
72 * clear the interrupt once the interrupt service routine is complete. It's
73 * write-only, writing any values to this register clears the interrupt, but
74 * reading is not permitted.
75 *
76 * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling
77 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
78 * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value
is
79 * inverted compared to the former one.
80 *
81 * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register,
82 * which contains bits indicating the reason for most recent CPU reset. If
83 * present, driver will use this register to check if previous reboot was due to
84 * watchdog timer reset.
85 *
86 * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE
87 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
88 * corresponding processor is in reset state.
89 *
90 * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT)
91 * with "watchdog counter enable" bit. That bit should be set to make
watchdog
92 * counter running.
93 */
94 #define QUIRK_HAS_WTCLRINT_REG (1 << 0)
95 #define QUIRK_HAS_PMU_MASK_RESET (1 << 1)
96 #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
97 #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
98 #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
99
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org