[kbuild-all] [android-common:android-4.19 1/4] drivers/pwm/pwm-stm32-lp.c:63:3: warning: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'u64'

tree: https://android.googlesource.com/kernel/common android-4.19 head: b12d8a020f80c15f34bb430628d6ecdba289e72b commit: d892c9f3571faa2e691fc3a9eb6ea4f4da1d7eab [1/4] ANDROID: GKI: pwm: core: Add option to config PWM duty/period with u64 data length config: i386-randconfig-a006-20200615 (attached as .config) compiler: gcc-4.9 (Ubuntu 4.9.3-13ubuntu2) 4.9.3 reproduce (this is a W=1 build): git checkout d892c9f3571faa2e691fc3a9eb6ea4f4da1d7eab # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): drivers/pwm/pwm-stm32-lp.c: In function 'stm32_pwm_lp_apply': dev_dbg(priv->chip.dev, "Can't reach %u nsn", state->period); ^ vim +63 drivers/pwm/pwm-stm32-lp.c e70a540b4e0230 Fabrice Gasnier 2017-08-28 32 e70a540b4e0230 Fabrice Gasnier 2017-08-28 33 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, e70a540b4e0230 Fabrice Gasnier 2017-08-28 34 struct pwm_state *state) e70a540b4e0230 Fabrice Gasnier 2017-08-28 35 { e70a540b4e0230 Fabrice Gasnier 2017-08-28 36 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); e70a540b4e0230 Fabrice Gasnier 2017-08-28 37 unsigned long long prd, div, dty; e70a540b4e0230 Fabrice Gasnier 2017-08-28 38 struct pwm_state cstate; e70a540b4e0230 Fabrice Gasnier 2017-08-28 39 u32 val, mask, cfgr, presc = 0; e70a540b4e0230 Fabrice Gasnier 2017-08-28 40 bool reenable; e70a540b4e0230 Fabrice Gasnier 2017-08-28 41 int ret; e70a540b4e0230 Fabrice Gasnier 2017-08-28 42 e70a540b4e0230 Fabrice Gasnier 2017-08-28 43 pwm_get_state(pwm, &cstate); e70a540b4e0230 Fabrice Gasnier 2017-08-28 44 reenable = !cstate.enabled; e70a540b4e0230 Fabrice Gasnier 2017-08-28 45 e70a540b4e0230 Fabrice Gasnier 2017-08-28 46 if (!state->enabled) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 47 if (cstate.enabled) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 48 /* Disable LP timer */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 49 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); e70a540b4e0230 Fabrice Gasnier 2017-08-28 50 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 51 return ret; e70a540b4e0230 Fabrice Gasnier 2017-08-28 52 /* disable clock to PWM counter */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 53 clk_disable(priv->clk); e70a540b4e0230 Fabrice Gasnier 2017-08-28 54 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 55 return 0; e70a540b4e0230 Fabrice Gasnier 2017-08-28 56 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 57 e70a540b4e0230 Fabrice Gasnier 2017-08-28 58 /* Calculate the period and prescaler value */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 59 div = (unsigned long long)clk_get_rate(priv->clk) * state->period; e70a540b4e0230 Fabrice Gasnier 2017-08-28 60 do_div(div, NSEC_PER_SEC); 65348659535d23 Fabrice Gasnier 2019-09-18 61 if (!div) { 65348659535d23 Fabrice Gasnier 2019-09-18 62 /* Clock is too slow to achieve requested period. */ 65348659535d23 Fabrice Gasnier 2019-09-18 @63 dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period); 65348659535d23 Fabrice Gasnier 2019-09-18 64 return -EINVAL; 65348659535d23 Fabrice Gasnier 2019-09-18 65 } 65348659535d23 Fabrice Gasnier 2019-09-18 66 e70a540b4e0230 Fabrice Gasnier 2017-08-28 67 prd = div; e70a540b4e0230 Fabrice Gasnier 2017-08-28 68 while (div > STM32_LPTIM_MAX_ARR) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 69 presc++; e70a540b4e0230 Fabrice Gasnier 2017-08-28 70 if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 71 dev_err(priv->chip.dev, "max prescaler exceeded\n"); e70a540b4e0230 Fabrice Gasnier 2017-08-28 72 return -EINVAL; e70a540b4e0230 Fabrice Gasnier 2017-08-28 73 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 74 div = prd >> presc; e70a540b4e0230 Fabrice Gasnier 2017-08-28 75 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 76 prd = div; e70a540b4e0230 Fabrice Gasnier 2017-08-28 77 e70a540b4e0230 Fabrice Gasnier 2017-08-28 78 /* Calculate the duty cycle */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 79 dty = prd * state->duty_cycle; e70a540b4e0230 Fabrice Gasnier 2017-08-28 80 do_div(dty, state->period); e70a540b4e0230 Fabrice Gasnier 2017-08-28 81 e70a540b4e0230 Fabrice Gasnier 2017-08-28 82 if (!cstate.enabled) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 83 /* enable clock to drive PWM counter */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 84 ret = clk_enable(priv->clk); e70a540b4e0230 Fabrice Gasnier 2017-08-28 85 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 86 return ret; e70a540b4e0230 Fabrice Gasnier 2017-08-28 87 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 88 e70a540b4e0230 Fabrice Gasnier 2017-08-28 89 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); e70a540b4e0230 Fabrice Gasnier 2017-08-28 90 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 91 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 92 e70a540b4e0230 Fabrice Gasnier 2017-08-28 93 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || e70a540b4e0230 Fabrice Gasnier 2017-08-28 94 (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 95 val = FIELD_PREP(STM32_LPTIM_PRESC, presc); e70a540b4e0230 Fabrice Gasnier 2017-08-28 96 val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); e70a540b4e0230 Fabrice Gasnier 2017-08-28 97 mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; e70a540b4e0230 Fabrice Gasnier 2017-08-28 98 e70a540b4e0230 Fabrice Gasnier 2017-08-28 99 /* Must disable LP timer to modify CFGR */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 100 reenable = true; e70a540b4e0230 Fabrice Gasnier 2017-08-28 101 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); e70a540b4e0230 Fabrice Gasnier 2017-08-28 102 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 103 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 104 e70a540b4e0230 Fabrice Gasnier 2017-08-28 105 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, e70a540b4e0230 Fabrice Gasnier 2017-08-28 106 val); e70a540b4e0230 Fabrice Gasnier 2017-08-28 107 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 108 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 109 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 110 e70a540b4e0230 Fabrice Gasnier 2017-08-28 111 if (reenable) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 112 /* Must (re)enable LP timer to modify CMP & ARR */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 113 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, e70a540b4e0230 Fabrice Gasnier 2017-08-28 114 STM32_LPTIM_ENABLE); e70a540b4e0230 Fabrice Gasnier 2017-08-28 115 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 116 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 117 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 118 e70a540b4e0230 Fabrice Gasnier 2017-08-28 119 ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1); e70a540b4e0230 Fabrice Gasnier 2017-08-28 120 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 121 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 122 e70a540b4e0230 Fabrice Gasnier 2017-08-28 123 ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); e70a540b4e0230 Fabrice Gasnier 2017-08-28 124 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 125 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 126 e70a540b4e0230 Fabrice Gasnier 2017-08-28 127 /* ensure CMP & ARR registers are properly written */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 128 ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, e70a540b4e0230 Fabrice Gasnier 2017-08-28 129 (val & STM32_LPTIM_CMPOK_ARROK), e70a540b4e0230 Fabrice Gasnier 2017-08-28 130 100, 1000); e70a540b4e0230 Fabrice Gasnier 2017-08-28 131 if (ret) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 132 dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); e70a540b4e0230 Fabrice Gasnier 2017-08-28 133 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 134 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 135 ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, e70a540b4e0230 Fabrice Gasnier 2017-08-28 136 STM32_LPTIM_CMPOKCF_ARROKCF); e70a540b4e0230 Fabrice Gasnier 2017-08-28 137 if (ret) e70a540b4e0230 Fabrice Gasnier 2017-08-28 138 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 139 e70a540b4e0230 Fabrice Gasnier 2017-08-28 140 if (reenable) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 141 /* Start LP timer in continuous mode */ e70a540b4e0230 Fabrice Gasnier 2017-08-28 142 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR, e70a540b4e0230 Fabrice Gasnier 2017-08-28 143 STM32_LPTIM_CNTSTRT, e70a540b4e0230 Fabrice Gasnier 2017-08-28 144 STM32_LPTIM_CNTSTRT); e70a540b4e0230 Fabrice Gasnier 2017-08-28 145 if (ret) { e70a540b4e0230 Fabrice Gasnier 2017-08-28 146 regmap_write(priv->regmap, STM32_LPTIM_CR, 0); e70a540b4e0230 Fabrice Gasnier 2017-08-28 147 goto err; e70a540b4e0230 Fabrice Gasnier 2017-08-28 148 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 149 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 150 e70a540b4e0230 Fabrice Gasnier 2017-08-28 151 return 0; e70a540b4e0230 Fabrice Gasnier 2017-08-28 152 err: e70a540b4e0230 Fabrice Gasnier 2017-08-28 153 if (!cstate.enabled) e70a540b4e0230 Fabrice Gasnier 2017-08-28 154 clk_disable(priv->clk); e70a540b4e0230 Fabrice Gasnier 2017-08-28 155 e70a540b4e0230 Fabrice Gasnier 2017-08-28 156 return ret; e70a540b4e0230 Fabrice Gasnier 2017-08-28 157 } e70a540b4e0230 Fabrice Gasnier 2017-08-28 158 :::::: The code at line 63 was first introduced by commit :::::: 65348659535d23e6fb7a79aa9d54332479cf980e pwm: stm32-lp: Add check in case requested period cannot be achieved :::::: TO: Fabrice Gasnier <fabrice.gasnier(a)st.com&gt; :::::: CC: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org