[kbuild-all] drivers/pci/controller/pci-v3-semi.c:808:2-9: line 808 is redundant because platform_get_irq() already prints an error (fwd)

Unneeded warning message on failure of platform_get_irq. julia ---------- Forwarded message ---------- Date: Thu, 16 Jul 2020 08:05:55 +0800 From: kernel test robot <lkp(a)intel.com&gt; To: kbuild(a)lists.01.org Cc: lkp(a)intel.com, Julia Lawall <julia.lawall(a)lip6.fr&gt; Subject: drivers/pci/controller/pci-v3-semi.c:808:2-9: line 808 is redundant because platform_get_irq() already prints an error CC: kbuild-all(a)lists.01.org CC: linux-kernel(a)vger.kernel.org TO: YueHaibing <yuehaibing(a)huawei.com&gt; CC: "Greg Kroah-Hartman" <gregkh(a)linuxfoundation.org&gt; CC: Stephen Boyd <swboyd(a)chromium.org&gt; tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: e9919e11e219eaa5e8041b7b1a196839143e9125 commit: ca7ce5a2710ad2a57bf7d0c4c712590bb69a5e1c coccinelle: platform_get_irq: Fix parse error date: 10 months ago :::::: branch date: 2 days ago :::::: commit date: 10 months ago config: arm-randconfig-c021-20200715 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; Reported-by: Julia Lawall <julia.lawall(a)lip6.fr&gt; coccinelle warnings: (new ones prefixed by >>) # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit... git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git remote update linus git checkout ca7ce5a2710ad2a57bf7d0c4c712590bb69a5e1c vim +808 drivers/pci/controller/pci-v3-semi.c 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 730 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 731 static int v3_pci_probe(struct platform_device *pdev) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 732 { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 733 struct device *dev = &pdev->dev; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 734 struct device_node *np = dev->of_node; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 735 resource_size_t io_base; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 736 struct resource *regs; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 737 struct resource_entry *win; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 738 struct v3_pci *v3; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 739 struct pci_host_bridge *host; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 740 struct clk *clk; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 741 u16 val; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 742 int irq; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 743 int ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 744 LIST_HEAD(res); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 745 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 746 host = pci_alloc_host_bridge(sizeof(*v3)); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 747 if (!host) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 748 return -ENOMEM; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 749 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 750 host->dev.parent = dev; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 751 host->ops = &v3_pci_ops; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 752 host->busnr = 0; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 753 host->msi = NULL; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 754 host->map_irq = of_irq_parse_and_map_pci; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 755 host->swizzle_irq = pci_common_swizzle; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 756 v3 = pci_host_bridge_priv(host); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 757 host->sysdata = v3; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 758 v3->dev = dev; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 759 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 760 /* Get and enable host clock */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 761 clk = devm_clk_get(dev, NULL); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 762 if (IS_ERR(clk)) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 763 dev_err(dev, "clock not found\n"); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 764 return PTR_ERR(clk); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 765 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 766 ret = clk_prepare_enable(clk); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 767 if (ret) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 768 dev_err(dev, "unable to enable clock\n"); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 769 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 770 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 771 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 772 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 773 v3->base = devm_ioremap_resource(dev, regs); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 774 if (IS_ERR(v3->base)) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 775 return PTR_ERR(v3->base); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 776 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 777 * The hardware has a register with the physical base address 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 778 * of the V3 controller itself, verify that this is the same 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 779 * as the physical memory we've remapped it from. 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 780 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 781 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 782 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n", 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 783 readl(v3->base + V3_LB_IO_BASE), regs); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 784 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 785 /* Configuration space is 16MB directly mapped */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 786 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 787 if (resource_size(regs) != SZ_16M) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 788 dev_err(dev, "config mem is not 16MB!\n"); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 789 return -EINVAL; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 790 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 791 v3->config_mem = regs->start; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 792 v3->config_base = devm_ioremap_resource(dev, regs); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 793 if (IS_ERR(v3->config_base)) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 794 return PTR_ERR(v3->config_base); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 795 5bd51b35c7cbbc9 drivers/pci/host/pci-v3-semi.c Jan Kiszka 2018-05-15 796 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res, 055f87a2a336409 drivers/pci/host/pci-v3-semi.c Jan Kiszka 2018-05-15 797 &io_base); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 798 if (ret) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 799 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 800 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 801 ret = devm_request_pci_bus_resources(dev, &res); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 802 if (ret) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 803 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 804 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 805 /* Get and request error IRQ resource */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 806 irq = platform_get_irq(pdev, 0); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 807 if (irq <= 0) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 @808 dev_err(dev, "unable to obtain PCIv3 error IRQ\n"); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 809 return -ENODEV; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 810 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 811 ret = devm_request_irq(dev, irq, v3_irq, 0, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 812 "PCIv3 error", v3); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 813 if (ret < 0) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 814 dev_err(dev, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 815 "unable to request PCIv3 error IRQ %d (%d)\n", 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 816 irq, ret); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 817 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 818 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 819 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 820 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 821 * Unlock V3 registers, but only if they were previously locked. 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 822 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 823 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 824 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 825 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 826 /* Disable all slave access while we set up the windows */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 827 val = readw(v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 828 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 829 writew(val, v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 830 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 831 /* Put the PCI bus into reset */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 832 val = readw(v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 833 val &= ~V3_SYSTEM_M_RST_OUT; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 834 writew(val, v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 835 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 836 /* Retry until we're ready */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 837 val = readw(v3->base + V3_PCI_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 838 val |= V3_PCI_CFG_M_RETRY_EN; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 839 writew(val, v3->base + V3_PCI_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 840 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 841 /* Set up the local bus protocol */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 842 val = readw(v3->base + V3_LB_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 843 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 844 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 845 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 846 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 847 writew(val, v3->base + V3_LB_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 848 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 849 /* Enable the PCI bus master */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 850 val = readw(v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 851 val |= PCI_COMMAND_MASTER; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 852 writew(val, v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 853 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 854 /* Get the I/O and memory ranges from DT */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 855 resource_list_for_each_entry(win, &res) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 856 ret = v3_pci_setup_resource(v3, io_base, host, win); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 857 if (ret) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 858 dev_err(dev, "error setting up resources\n"); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 859 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 860 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 861 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 862 ret = v3_pci_parse_map_dma_ranges(v3, np); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 863 if (ret) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 864 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 865 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 866 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 867 * Disable PCI to host IO cycles, enable I/O buffers @3.3V, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 868 * set AD_LOW0 to 1 if one of the LB_MAP registers choose 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 869 * to use this (should be unused). 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 870 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 871 writel(0x00000000, v3->base + V3_PCI_IO_BASE); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 872 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS | 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 873 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 874 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 875 * DMA read and write from PCI bus commands types 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 876 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 877 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 878 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 879 writew(val, v3->base + V3_PCI_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 880 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 881 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 882 * Set the V3 FIFO such that writes have higher priority than 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 883 * reads, and local bus write causes local bus read fifo flush 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 884 * on aperture 1. Same for PCI. 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 885 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 886 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 | 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 887 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 | 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 888 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 | 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 889 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 890 v3->base + V3_FIFO_PRIORITY); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 891 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 892 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 893 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 894 * Clear any error interrupts, and enable parity and write error 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 895 * interrupts 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 896 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 897 writeb(0, v3->base + V3_LB_ISTAT); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 898 val = readw(v3->base + V3_LB_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 899 val |= V3_LB_CFG_LB_LB_INT; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 900 writew(val, v3->base + V3_LB_CFG); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 901 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 902 v3->base + V3_LB_IMASK); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 903 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 904 /* Special Integrator initialization */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 905 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 906 ret = v3_integrator_init(v3); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 907 if (ret) 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 908 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 909 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 910 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 911 /* Post-init: enable PCI memory and invalidate (master already on) */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 912 val = readw(v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 913 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 914 writew(val, v3->base + V3_PCI_CMD); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 915 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 916 /* Clear pending interrupts */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 917 writeb(0, v3->base + V3_LB_ISTAT); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 918 /* Read or write errors and parity errors cause interrupts */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 919 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR, 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 920 v3->base + V3_LB_IMASK); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 921 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 922 /* Take the PCI bus out of reset so devices can initialize */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 923 val = readw(v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 924 val |= V3_SYSTEM_M_RST_OUT; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 925 writew(val, v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 926 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 927 /* 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 928 * Re-lock the system register. 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 929 */ 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 930 val = readw(v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 931 val |= V3_SYSTEM_M_LOCK; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 932 writew(val, v3->base + V3_SYSTEM); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 933 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 934 list_splice_init(&res, &host->windows); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 935 ret = pci_scan_root_bus_bridge(host); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 936 if (ret) { 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 937 dev_err(dev, "failed to register host: %d\n", ret); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 938 return ret; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 939 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 940 v3->bus = host->bus; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 941 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 942 pci_bus_assign_resources(v3->bus); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 943 pci_bus_add_devices(v3->bus); 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 944 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 945 return 0; 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 946 } 68a15eb7bd0cf18 drivers/pci/host/pci-v3-semi.c Linus Walleij 2017-09-26 947 :::::: The code at line 808 was first introduced by commit :::::: 68a15eb7bd0cf180eb214c79aa4e1662c5eeb97c PCI: v3-semi: Add V3 Semiconductor PCI host driver :::::: TO: Linus Walleij <linus.walleij(a)linaro.org&gt; :::::: CC: Bjorn Helgaas <bhelgaas(a)google.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org