8:58 p.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: e28c0d7c92c89016c12a677616668957351e7542
commit: 709c27730a11d6681297d733eb8ee18166e9c38a drm/mcde: Fix display data flow control
config: i386-randconfig-m021-20201115 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com>
New smatch warnings:
drivers/gpu/drm/mcde/mcde_display.c:543 mcde_configure_channel() error: uninitialized
symbol 'val'.
vim +/val +543 drivers/gpu/drm/mcde/mcde_display.c
5fc537bfd00033a Linus Walleij 2019-05-24 458 static void mcde_configure_channel(struct
mcde *mcde, enum mcde_channel ch,
5fc537bfd00033a Linus Walleij 2019-05-24 459 enum mcde_fifo fifo,
5fc537bfd00033a Linus Walleij 2019-05-24 460 const struct drm_display_mode
*mode)
5fc537bfd00033a Linus Walleij 2019-05-24 461 {
5fc537bfd00033a Linus Walleij 2019-05-24 462 u32 val;
5fc537bfd00033a Linus Walleij 2019-05-24 463 u32 conf;
5fc537bfd00033a Linus Walleij 2019-05-24 464 u32 sync;
5fc537bfd00033a Linus Walleij 2019-05-24 465 u32 stat;
5fc537bfd00033a Linus Walleij 2019-05-24 466 u32 bgcol;
5fc537bfd00033a Linus Walleij 2019-05-24 467 u32 mux;
5fc537bfd00033a Linus Walleij 2019-05-24 468
5fc537bfd00033a Linus Walleij 2019-05-24 469 switch (ch) {
5fc537bfd00033a Linus Walleij 2019-05-24 470 case MCDE_CHANNEL_0:
5fc537bfd00033a Linus Walleij 2019-05-24 471 conf = MCDE_CHNL0CONF;
5fc537bfd00033a Linus Walleij 2019-05-24 472 sync = MCDE_CHNL0SYNCHMOD;
5fc537bfd00033a Linus Walleij 2019-05-24 473 stat = MCDE_CHNL0STAT;
5fc537bfd00033a Linus Walleij 2019-05-24 474 bgcol = MCDE_CHNL0BCKGNDCOL;
5fc537bfd00033a Linus Walleij 2019-05-24 475 mux = MCDE_CHNL0MUXING;
5fc537bfd00033a Linus Walleij 2019-05-24 476 break;
5fc537bfd00033a Linus Walleij 2019-05-24 477 case MCDE_CHANNEL_1:
5fc537bfd00033a Linus Walleij 2019-05-24 478 conf = MCDE_CHNL1CONF;
5fc537bfd00033a Linus Walleij 2019-05-24 479 sync = MCDE_CHNL1SYNCHMOD;
5fc537bfd00033a Linus Walleij 2019-05-24 480 stat = MCDE_CHNL1STAT;
5fc537bfd00033a Linus Walleij 2019-05-24 481 bgcol = MCDE_CHNL1BCKGNDCOL;
5fc537bfd00033a Linus Walleij 2019-05-24 482 mux = MCDE_CHNL1MUXING;
5fc537bfd00033a Linus Walleij 2019-05-24 483 break;
5fc537bfd00033a Linus Walleij 2019-05-24 484 case MCDE_CHANNEL_2:
5fc537bfd00033a Linus Walleij 2019-05-24 485 conf = MCDE_CHNL2CONF;
5fc537bfd00033a Linus Walleij 2019-05-24 486 sync = MCDE_CHNL2SYNCHMOD;
5fc537bfd00033a Linus Walleij 2019-05-24 487 stat = MCDE_CHNL2STAT;
5fc537bfd00033a Linus Walleij 2019-05-24 488 bgcol = MCDE_CHNL2BCKGNDCOL;
5fc537bfd00033a Linus Walleij 2019-05-24 489 mux = MCDE_CHNL2MUXING;
5fc537bfd00033a Linus Walleij 2019-05-24 490 break;
5fc537bfd00033a Linus Walleij 2019-05-24 491 case MCDE_CHANNEL_3:
5fc537bfd00033a Linus Walleij 2019-05-24 492 conf = MCDE_CHNL3CONF;
5fc537bfd00033a Linus Walleij 2019-05-24 493 sync = MCDE_CHNL3SYNCHMOD;
5fc537bfd00033a Linus Walleij 2019-05-24 494 stat = MCDE_CHNL3STAT;
5fc537bfd00033a Linus Walleij 2019-05-24 495 bgcol = MCDE_CHNL3BCKGNDCOL;
5fc537bfd00033a Linus Walleij 2019-05-24 496 mux = MCDE_CHNL3MUXING;
5fc537bfd00033a Linus Walleij 2019-05-24 497 return;
5fc537bfd00033a Linus Walleij 2019-05-24 498 }
5fc537bfd00033a Linus Walleij 2019-05-24 499
5fc537bfd00033a Linus Walleij 2019-05-24 500 /* Set up channel 0 sync (based on
chnl_update_registers()) */
709c27730a11d66 Linus Walleij 2020-07-29 501 switch (mcde->flow_mode) {
709c27730a11d66 Linus Walleij 2020-07-29 502 case MCDE_COMMAND_ONESHOT_FLOW:
709c27730a11d66 Linus Walleij 2020-07-29 503 /* Oneshot is achieved with software
sync */
709c27730a11d66 Linus Walleij 2020-07-29 504 val =
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE
709c27730a11d66 Linus Walleij 2020-07-29 505 <<
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 506 break;
709c27730a11d66 Linus Walleij 2020-07-29 507 case MCDE_COMMAND_TE_FLOW:
5fc537bfd00033a Linus Walleij 2019-05-24 508 val =
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
5fc537bfd00033a Linus Walleij 2019-05-24 509 <<
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 510 val |=
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
709c27730a11d66 Linus Walleij 2020-07-29 511 <<
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 512 break;
709c27730a11d66 Linus Walleij 2020-07-29 513 case MCDE_COMMAND_BTA_TE_FLOW:
709c27730a11d66 Linus Walleij 2020-07-29 514 val =
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
709c27730a11d66 Linus Walleij 2020-07-29 515 <<
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 516 /*
709c27730a11d66 Linus Walleij 2020-07-29 517 * TODO:
709c27730a11d66 Linus Walleij 2020-07-29 518 * The vendor driver uses the formatter
as sync source
709c27730a11d66 Linus Walleij 2020-07-29 519 * for BTA TE mode. Test to use TE if
you have a panel
709c27730a11d66 Linus Walleij 2020-07-29 520 * that uses this mode.
709c27730a11d66 Linus Walleij 2020-07-29 521 */
709c27730a11d66 Linus Walleij 2020-07-29 522 val |=
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
709c27730a11d66 Linus Walleij 2020-07-29 523 <<
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 524 break;
709c27730a11d66 Linus Walleij 2020-07-29 525 case MCDE_VIDEO_TE_FLOW:
709c27730a11d66 Linus Walleij 2020-07-29 526 val =
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
5fc537bfd00033a Linus Walleij 2019-05-24 527 <<
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
d920e8da3d837bc Stephan Gerhold 2019-11-06 528 val |=
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
d920e8da3d837bc Stephan Gerhold 2019-11-06 529 <<
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 530 break;
709c27730a11d66 Linus Walleij 2020-07-29 531 case MCDE_VIDEO_FORMATTER_FLOW:
709c27730a11d66 Linus Walleij 2020-07-29 532 val =
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
709c27730a11d66 Linus Walleij 2020-07-29 533 <<
MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
5fc537bfd00033a Linus Walleij 2019-05-24 534 val |=
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
5fc537bfd00033a Linus Walleij 2019-05-24 535 <<
MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
709c27730a11d66 Linus Walleij 2020-07-29 536 break;
709c27730a11d66 Linus Walleij 2020-07-29 537 default:
709c27730a11d66 Linus Walleij 2020-07-29 538 dev_err(mcde->dev, "unknown
flow mode %d\n",
709c27730a11d66 Linus Walleij 2020-07-29 539 mcde->flow_mode);
709c27730a11d66 Linus Walleij 2020-07-29 540 break;
Not initialized on this path
709c27730a11d66 Linus Walleij 2020-07-29 541 }
d920e8da3d837bc Stephan Gerhold 2019-11-06 542
5fc537bfd00033a Linus Walleij 2019-05-24 @543 writel(val, mcde->regs + sync);
^^^
5fc537bfd00033a Linus Walleij 2019-05-24 544
5fc537bfd00033a Linus Walleij 2019-05-24 545 /* Set up pixels per line and lines per
frame */
5fc537bfd00033a Linus Walleij 2019-05-24 546 val = (mode->hdisplay - 1) <<
MCDE_CHNLXCONF_PPL_SHIFT;
5fc537bfd00033a Linus Walleij 2019-05-24 547 val |= (mode->vdisplay - 1) <<
MCDE_CHNLXCONF_LPF_SHIFT;
5fc537bfd00033a Linus Walleij 2019-05-24 548 writel(val, mcde->regs + conf);
5fc537bfd00033a Linus Walleij 2019-05-24 549
5fc537bfd00033a Linus Walleij 2019-05-24 550 /*
5fc537bfd00033a Linus Walleij 2019-05-24 551 * Normalize color conversion:
5fc537bfd00033a Linus Walleij 2019-05-24 552 * black background, OLED conversion
disable on channel
5fc537bfd00033a Linus Walleij 2019-05-24 553 */
5fc537bfd00033a Linus Walleij 2019-05-24 554 val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN |
5fc537bfd00033a Linus Walleij 2019-05-24 555 MCDE_CHNLXSTAT_CHNLRD;
5fc537bfd00033a Linus Walleij 2019-05-24 556 writel(val, mcde->regs + stat);
5fc537bfd00033a Linus Walleij 2019-05-24 557 writel(0, mcde->regs + bgcol);
5fc537bfd00033a Linus Walleij 2019-05-24 558
5fc537bfd00033a Linus Walleij 2019-05-24 559 /* Set up muxing: connect the channel to
the desired FIFO */
5fc537bfd00033a Linus Walleij 2019-05-24 560 switch (fifo) {
5fc537bfd00033a Linus Walleij 2019-05-24 561 case MCDE_FIFO_A:
5fc537bfd00033a Linus Walleij 2019-05-24 562
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_A,
5fc537bfd00033a Linus Walleij 2019-05-24 563 mcde->regs + mux);
5fc537bfd00033a Linus Walleij 2019-05-24 564 break;
5fc537bfd00033a Linus Walleij 2019-05-24 565 case MCDE_FIFO_B:
5fc537bfd00033a Linus Walleij 2019-05-24 566
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_B,
5fc537bfd00033a Linus Walleij 2019-05-24 567 mcde->regs + mux);
5fc537bfd00033a Linus Walleij 2019-05-24 568 break;
5fc537bfd00033a Linus Walleij 2019-05-24 569 }
5fc537bfd00033a Linus Walleij 2019-05-24 570 }
---
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