[kbuild-all] [skeggsb:03.00-disp 44/65] drivers/gpu/drm/nouveau/dispnv50/disp.c:782:3: warning: variable 'config' is uninitialized when used here

tree: https://github.com/skeggsb/linux 03.00-disp head: 9d141f4c5d74118aa6e66daa9fde389857627d89 commit: 6e294797f27c6dac80ca1f4acd046151056ecccf [44/65] drm/nouveau/disp: move HDMI config into acquire + infoframe methods config: riscv-randconfig-r022-20211014 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project acb3b187c4c88650a6a717a1bcb234d27d0d7f54) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/skeggsb/linux/commit/6e294797f27c6dac80ca1f4acd0461510... git remote add skeggsb https://github.com/skeggsb/linux git fetch --no-tags skeggsb 03.00-disp git checkout 6e294797f27c6dac80ca1f4acd046151056ecccf # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=riscv If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); ^~~~~~ drivers/gpu/drm/nouveau/dispnv50/disp.c:759:11: note: initialize the variable 'config' to silence this warning u8 config, scdc = 0; ^ = '\0' drivers/gpu/drm/nouveau/dispnv50/disp.c:2607:1: warning: no previous prototype for function 'nv50_display_create' [-Wmissing-prototypes] nv50_display_create(struct drm_device *dev) ^ drivers/gpu/drm/nouveau/dispnv50/disp.c:2606:1: note: declare 'static' if the function is not intended to be used outside of this translation unit int ^ static 2 warnings generated. vim +/config +782 drivers/gpu/drm/nouveau/dispnv50/disp.c 78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 745 f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 746 /****************************************************************************** f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 747 * HDMI f20c665ca04a95 drivers/gpu/drm/nouveau/nv50_display.c Ben Skeggs 2016-11-04 748 *****************************************************************************/ 78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 749 static void 1b38cf6b03e92e drivers/gpu/drm/nouveau/dispnv50/disp.c Lyude Paul 2020-11-13 750 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 1b38cf6b03e92e drivers/gpu/drm/nouveau/dispnv50/disp.c Lyude Paul 2020-11-13 751 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 752 struct drm_display_mode *mode, bool hda) 78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 753 { 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 754 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 755 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 756 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 757 union hdmi_infoframe infoframe; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 758 const u8 rekey = 56; /* binary driver, and tegra, constant */ 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 759 u8 config, scdc = 0; 64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 760 u32 max_ac_packet; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 761 struct { 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 762 struct nvif_outp_infoframe_v0 infoframe; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 763 u8 data[17]; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 764 } args; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 765 int ret, size; 34fd3e5d8c5f6b drivers/gpu/drm/nouveau/nv50_display.c Alastair Bridgewater 2017-04-11 766 64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 767 max_ac_packet = mode->htotal - mode->hdisplay; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 768 max_ac_packet -= rekey; 64d9cc04ec08d3 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 769 max_ac_packet -= 18; /* constant from tegra */ 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 770 max_ac_packet /= 32; 091e40cd952996 drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 771 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 772 if (hdmi->scdc.scrambling.supported) { 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 773 const bool high_tmds_clock_ratio = mode->clock > 340000; 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 774 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 775 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 776 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc); 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 777 if (ret < 0) { 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 778 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 779 return; 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 780 } 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 781 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 @782 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 783 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 784 config |= SCDC_SCRAMBLING_ENABLE; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 785 if (high_tmds_clock_ratio) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 786 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 787 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 788 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 789 if (ret < 0) 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 790 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 7a406f8a62ff0a drivers/gpu/drm/nouveau/dispnv50/disp.c Ilia Mirkin 2018-09-03 791 config, ret); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 792 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 793 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 794 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_SCRAMBLE; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 795 if (high_tmds_clock_ratio) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 796 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_DIV_BY_4; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 797 } 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 798 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 799 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true, 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 800 max_ac_packet, rekey, scdc, hda); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 801 if (ret) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 802 return; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 803 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 804 /* AVI InfoFrame. */ 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 805 args.infoframe.version = 0; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 806 args.infoframe.head = nv_crtc->index; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 807 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 808 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 809 size = hdmi_infoframe_pack(&infoframe, args.data, 17); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 810 else 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 811 size = 0; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 812 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 813 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 814 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 815 /* Vendor InfoFrame. */ 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 816 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi, 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 817 &nv_connector->base, mode)) 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 818 size = hdmi_infoframe_pack(&infoframe, args.data, 17); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 819 else 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 820 size = 0; 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 821 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 822 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size); 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 823 6e294797f27c6d drivers/gpu/drm/nouveau/dispnv50/disp.c Ben Skeggs 2021-03-02 824 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 825 } 78951d2226e13d drivers/gpu/drm/nouveau/nvd0_display.c Ben Skeggs 2011-11-11 826 :::::: The code at line 782 was first introduced by commit :::::: 7a406f8a62ff0a3647f96f0cfdb518a99a01bf3f drm/nouveau/disp: add support for setting scdc parameters for high modes :::::: TO: Ilia Mirkin <imirkin(a)alum.mit.edu&gt; :::::: CC: Ben Skeggs <bskeggs(a)redhat.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org