tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 860461e4fcaa76200d2d1a53523e0ff7be92e6e8 commit: fec38565411f968a8d8ef207412da65857f2a636 [7459/8629] clk: samsung: Use cached clk_hws instead of __clk_lookup() calls config: arm-randconfig-r013-20200917 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 1321160a26e7e489baf9b10d6de90a342f898960) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi git checkout fec38565411f968a8d8ef207412da65857f2a636 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200, ^~~ drivers/clk/samsung/clk-exynos5420.c:1564:21: note: initialize the variable 'hws' to silence this warning struct clk_hw **hws; ^ = NULL 1 warning generated. # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commi... git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout fec38565411f968a8d8ef207412da65857f2a636 vim +/hws +1628 drivers/clk/samsung/clk-exynos5420.c 1558 1559 /* register exynos5420 clocks */ 1560 static void __init exynos5x_clk_init(struct device_node *np, 1561 enum exynos5x_soc soc) 1562 { 1563 struct samsung_clk_provider *ctx; 1564 struct clk_hw **hws; 1565 1566 if (np) { 1567 reg_base = of_iomap(np, 0); 1568 if (!reg_base) 1569 panic("%s: failed to map registers\n", __func__); 1570 } else { 1571 panic("%s: unable to determine soc\n", __func__); 1572 } 1573 1574 exynos5x_soc = soc; 1575 1576 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1577 1578 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1579 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1580 ext_clk_match); 1581 1582 if (_get_rate("fin_pll") == 24 * MHZ) { 1583 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1584 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1585 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1586 exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; 1587 } 1588 1589 if (soc == EXYNOS5420) 1590 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1591 else 1592 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 1593 1594 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1595 reg_base); 1596 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1597 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1598 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1599 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1600 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1601 ARRAY_SIZE(exynos5x_mux_clks)); 1602 samsung_clk_register_div(ctx, exynos5x_div_clks, 1603 ARRAY_SIZE(exynos5x_div_clks)); 1604 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1605 ARRAY_SIZE(exynos5x_gate_clks)); 1606 1607 if (soc == EXYNOS5420) { 1608 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1609 ARRAY_SIZE(exynos5420_mux_clks)); 1610 samsung_clk_register_div(ctx, exynos5420_div_clks, 1611 ARRAY_SIZE(exynos5420_div_clks)); 1612 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1613 ARRAY_SIZE(exynos5420_gate_clks)); 1614 } else { 1615 samsung_clk_register_fixed_factor( 1616 ctx, exynos5800_fixed_factor_clks, 1617 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1618 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1619 ARRAY_SIZE(exynos5800_mux_clks)); 1620 samsung_clk_register_div(ctx, exynos5800_div_clks, 1621 ARRAY_SIZE(exynos5800_div_clks)); 1622 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1623 ARRAY_SIZE(exynos5800_gate_clks)); 1624 } 1625 1626 if (soc == EXYNOS5420) { 1627 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1629 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 1630 } else { 1631 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1632 hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200, 1633 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 1634 } 1635 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1636 hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200, 1637 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1638 1639 samsung_clk_extended_sleep_init(reg_base, 1640 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 1641 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1642 1643 if (soc == EXYNOS5800) { 1644 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 1645 ARRAY_SIZE(exynos5800_clk_regs)); 1646 1647 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), 1648 exynos5800_subcmus); 1649 } else { 1650 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1651 exynos5x_subcmus); 1652 } 1653 1654 hws = ctx->clk_data.hws; 1655 /* 1656 * Keep top part of G3D clock path enabled permanently to ensure 1657 * that the internal busses get their clock regardless of the 1658 * main G3D clock enablement status. 1659 */ 1660 clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); 1661 /* 1662 * Keep top BPLL mux enabled permanently to ensure that DRAM operates 1663 * properly. 1664 */ 1665 clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); 1666 1667 samsung_clk_of_add_provider(np, ctx); 1668 } 1669 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org