tree: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git pci-dw-config-access head: 6273eefbdae51129a74b3baf3945da012ba8b1b6 commit: 56dfee88838769f43830a290fce0401876e513c0 [19/27] PCI: dwc: Simplify config space handling config: arm64-randconfig-r003-20200818 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 790878f291fa5dc58a1c560cb6cc76fd1bfd1c5a) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu git checkout 56dfee88838769f43830a290fce0401876e513c0 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All error/warnings (new ones prefixed by >>): else ^ { ^ drivers/pci/controller/dwc/pcie-designware-host.c:473:1: error: function definition is not allowed here { ^ .read = dw_pcie_rd_other_conf, ^ .write = dw_pcie_wr_other_conf, ^ drivers/pci/controller/dwc/pcie-designware-host.c:495:1: error: function definition is not allowed here { ^ drivers/pci/controller/dwc/pcie-designware-host.c:512:1: error: function definition is not allowed here { ^ EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); ^ drivers/pci/controller/dwc/pcie-designware-host.c:432:1: note: to match this '{' { ^ static struct pci_ops dw_child_pcie_ops = { ^ 1 warning and 8 errors generated. # https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?id... git remote add robh https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git git fetch --no-tags robh pci-dw-config-access git checkout 56dfee88838769f43830a290fce0401876e513c0 vim +443 drivers/pci/controller/dwc/pcie-designware-host.c 429 430 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 431 unsigned int devfn, int where) 432 { 433 int type; 434 u32 busdev; 435 struct pcie_port *pp = bus->sysdata; 436 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 437 438 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 439 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 440 441 if (pci_is_root_bus(bus->parent)) { 442 type = PCIE_ATU_TYPE_CFG0; 444 type = PCIE_ATU_TYPE_CFG1; 445 446 447 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 448 type, pp->cfg0_base, 449 busdev, pp->cfg0_size); 450 451 return pp->va_cfg0_base + where; 452 } 453 454 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 455 int where, int size, u32 *val) 457 int ret; 458 struct pcie_port *pp = bus->sysdata; 459 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 460 461 ret = pci_generic_config_read(bus, devfn, where, size, val); 462 463 if (!ret && pci->num_viewport <= 2) 464 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 465 PCIE_ATU_TYPE_IO, pp->io_base, 466 pp->io_bus_addr, pp->io_size); 467 468 return ret; 469 } 470 471 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 472 int where, int size, u32 val) 473 { 474 int ret; 475 struct pcie_port *pp = bus->sysdata; 476 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 477 478 ret = pci_generic_config_write(bus, devfn, where, size, val); 479 480 if (!ret && pci->num_viewport <= 2) 481 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 482 PCIE_ATU_TYPE_IO, pp->io_base, 483 pp->io_bus_addr, pp->io_size); 484 485 return ret; 486 } 487 489 .map_bus = dw_pcie_other_conf_map_bus, 492 }; 493 494 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 495 { 496 struct pcie_port *pp = bus->sysdata; 497 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 498 499 if (PCI_SLOT(devfn) > 0) 500 return NULL; 501 502 return pci->dbi_base + where; 503 } 504 505 static struct pci_ops dw_pcie_ops = { 506 .map_bus = dw_pcie_own_conf_map_bus, 507 .read = pci_generic_config_read, 508 .write = pci_generic_config_write, 509 }; 510 511 void dw_pcie_setup_rc(struct pcie_port *pp) 512 { 513 u32 val, ctrl, num_ctrls; 514 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 515 516 /* 517 * Enable DBI read-only registers for writing/updating configuration. 518 * Write permission gets disabled towards the end of this function. 519 */ 520 dw_pcie_dbi_ro_wr_en(pci); 521 522 dw_pcie_setup(pci); 523 524 if (!pp->ops->msi_host_init) { 525 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 526 527 /* Initialize IRQ Status array */ 528 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 529 pp->irq_mask[ctrl] = ~0; 530 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 531 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 532 pp->irq_mask[ctrl]); 533 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 534 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 535 ~0); 536 } 537 } 538 539 /* Setup RC BARs */ 540 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 541 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 542 543 /* Setup interrupt pins */ 544 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 545 val &= 0xffff00ff; 546 val |= 0x00000100; 547 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 548 549 /* Setup bus numbers */ 550 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 551 val &= 0xff000000; 552 val |= 0x00ff0100; 553 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 554 555 /* Setup command register */ 556 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 557 val &= 0xffff0000; 558 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 559 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 560 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 561 562 /* 563 * If the platform provides its own child bus config accesses, it means 564 * the platform uses its own address translation component rather than 565 * ATU, so we should not program the ATU here. 566 */ 567 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 568 struct resource_entry *entry = 569 resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 570 571 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, 572 PCIE_ATU_TYPE_MEM, entry->res->start, 573 entry->res->start - entry->offset, 574 resource_size(entry->res)); 575 if (pci->num_viewport > 2) 576 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, 577 PCIE_ATU_TYPE_IO, pp->io_base, 578 pp->io_bus_addr, pp->io_size); 579 } 580 581 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 582 583 /* Program correct class for RC */ 584 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 585 586 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 587 val |= PORT_LOGIC_SPEED_CHANGE; 588 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 589 590 dw_pcie_dbi_ro_wr_dis(pci); 591 } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org