tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 18250b538735142307082e4e99e3ae5c12d44013 commit: b45fdeab45bc42c2cd2dfbb3d11a3dd797907af6 [12579/13394] drm/amdgpu: Add graphics cache rinse packet for sdma config: i386-randconfig-m021-20210416 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; smatch warnings: drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:389 sdma_v5_2_ring_emit_mem_sync() warn: inconsistent indenting vim +389 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 371 372 /** 373 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 374 * 375 * @ring: amdgpu ring pointer 376 * @job: job to retrieve vmid from 377 * @ib: IB object to schedule 378 * 379 * flush the IB by graphics cache rinse. 380 */ 381 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 382 { 383 uint32_t gcr_cntl = 384 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 385 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 386 SDMA_GCR_GLI_INV(1); 387 388 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 390 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 391 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 392 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 393 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 394 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 395 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 396 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 397 } 398 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org