tree: https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git queue-5.4 head: d2c5af89e80c5b71f1da59879464a930947306a2 commit: e597d09e89f8a7ea76ebce97489beea3cc9267a7 [103/132] mei: me: emmitsburg workstation DID config: x86_64-randconfig-a005-20210318 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 436c6c9c20cc522c92a923440a5fc509c342a7db) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git/c... git remote add sashal-linux-stable https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git git fetch --no-tags sashal-linux-stable queue-5.4 git checkout e597d09e89f8a7ea76ebce97489beea3cc9267a7 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All error/warnings (new ones prefixed by >>): {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, ^~~~~~~~~~~~~~~~~~~~ MEI_ME_PCH8_SPS_CFG drivers/misc/mei/hw-me.h:36:34: note: expanded from macro 'MEI_PCI_DEVICE' .driver_data = (kernel_ulong_t)(cfg), ^ drivers/misc/mei/hw-me.h:87:2: note: 'MEI_ME_PCH8_SPS_CFG' declared here MEI_ME_PCH8_SPS_CFG, ^ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || ^~~~~~~~~~~~~~~~ include/linux/dma-mapping.h:142:54: note: expanded from macro 'DMA_BIT_MASK' #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ^ ~~~ drivers/misc/mei/pci-me.c:188:40: warning: shift count >= width of type [-Wshift-count-overflow] dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { ^~~~~~~~~~~~~~~~ include/linux/dma-mapping.h:142:54: note: expanded from macro 'DMA_BIT_MASK' #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ^ ~~~ 2 warnings and 1 error generated. vim +114 drivers/misc/mei/pci-me.c 34 35 /* mei_pci_tbl - PCI Device ID Table */ 36 static const struct pci_device_id mei_me_pci_tbl[] = { 37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, 38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, 39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, 40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, 41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, 42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, 43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, 44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, 45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, 46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, 47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, 48 49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, 50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, 51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, 52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, 53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, 54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, 55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, 56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, 57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, 58 59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, 60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, 61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, 62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, 63 64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, 65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, 66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, 67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, 68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 77 78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, 83 84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, 86 87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, 88 89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, 90 91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, 92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, 93 94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)}, 96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)}, 98 99 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 100 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, 101 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, 102 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, 103 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)}, 104 105 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 106 107 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)}, 108 109 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)}, 110 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, 111 112 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, 113 115 116 /* required last entry */ 117 {0, } 118 }; 119 120 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 121 122 #ifdef CONFIG_PM 123 static inline void mei_me_set_pm_domain(struct mei_device *dev); 124 static inline void mei_me_unset_pm_domain(struct mei_device *dev); 125 #else 126 static inline void mei_me_set_pm_domain(struct mei_device *dev) {} 127 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} 128 #endif /* CONFIG_PM */ 129 130 /** 131 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface 132 * 133 * @pdev: PCI device structure 134 * @cfg: per generation config 135 * 136 * Return: true if ME Interface is valid, false otherwise 137 */ 138 static bool mei_me_quirk_probe(struct pci_dev *pdev, 139 const struct mei_cfg *cfg) 140 { 141 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { 142 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 143 return false; 144 } 145 146 return true; 147 } 148 149 /** 150 * mei_me_probe - Device Initialization Routine 151 * 152 * @pdev: PCI device structure 153 * @ent: entry in kcs_pci_tbl 154 * 155 * Return: 0 on success, <0 on failure. 156 */ 157 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 158 { 159 const struct mei_cfg *cfg; 160 struct mei_device *dev; 161 struct mei_me_hw *hw; 162 unsigned int irqflags; 163 int err; 164 165 cfg = mei_me_get_cfg(ent->driver_data); 166 if (!cfg) 167 return -ENODEV; 168 169 if (!mei_me_quirk_probe(pdev, cfg)) 170 return -ENODEV; 171 172 /* enable pci dev */ 173 err = pcim_enable_device(pdev); 174 if (err) { 175 dev_err(&pdev->dev, "failed to enable pci device.\n"); 176 goto end; 177 } 178 /* set PCI host mastering */ 179 pci_set_master(pdev); 180 /* pci request regions and mapping IO device memory for mei driver */ 181 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); 182 if (err) { 183 dev_err(&pdev->dev, "failed to get pci regions.\n"); 184 goto end; 185 } 186 188 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 189 190 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 191 if (err) 192 err = dma_set_coherent_mask(&pdev->dev, 193 DMA_BIT_MASK(32)); 194 } 195 if (err) { 196 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 197 goto end; 198 } 199 200 /* allocates and initializes the mei dev structure */ 201 dev = mei_me_dev_init(pdev, cfg); 202 if (!dev) { 203 err = -ENOMEM; 204 goto end; 205 } 206 hw = to_me_hw(dev); 207 hw->mem_addr = pcim_iomap_table(pdev)[0]; 208 209 pci_enable_msi(pdev); 210 211 /* request and enable interrupt */ 212 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; 213 214 err = request_threaded_irq(pdev->irq, 215 mei_me_irq_quick_handler, 216 mei_me_irq_thread_handler, 217 irqflags, KBUILD_MODNAME, dev); 218 if (err) { 219 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 220 pdev->irq); 221 goto end; 222 } 223 224 if (mei_start(dev)) { 225 dev_err(&pdev->dev, "init hw failure.\n"); 226 err = -ENODEV; 227 goto release_irq; 228 } 229 230 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); 231 pm_runtime_use_autosuspend(&pdev->dev); 232 233 err = mei_register(dev, &pdev->dev); 234 if (err) 235 goto stop; 236 237 pci_set_drvdata(pdev, dev); 238 239 /* 240 * MEI requires to resume from runtime suspend mode 241 * in order to perform link reset flow upon system suspend. 242 */ 243 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 244 245 /* 246 * ME maps runtime suspend/resume to D0i states, 247 * hence we need to go around native PCI runtime service which 248 * eventually brings the device into D3cold/hot state, 249 * but the mei device cannot wake up from D3 unlike from D0i3. 250 * To get around the PCI device native runtime pm, 251 * ME uses runtime pm domain handlers which take precedence 252 * over the driver's pm handlers. 253 */ 254 mei_me_set_pm_domain(dev); 255 256 if (mei_pg_is_enabled(dev)) { 257 pm_runtime_put_noidle(&pdev->dev); 258 if (hw->d0i3_supported) 259 pm_runtime_allow(&pdev->dev); 260 } 261 262 dev_dbg(&pdev->dev, "initialization successful.\n"); 263 264 return 0; 265 266 stop: 267 mei_stop(dev); 268 release_irq: 269 mei_cancel_work(dev); 270 mei_disable_interrupts(dev); 271 free_irq(pdev->irq, dev); 272 end: 273 dev_err(&pdev->dev, "initialization failed.\n"); 274 return err; 275 } 276 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org