tree: https://github.com/miquelraynal/linux-0day.git perso/nand-next/flags head: c5212e24213cba25bcc57e3bbe0781f3e9d83611 commit: 9cbc57f82b025d7fcdfe329cd916be6a457d81d2 [96/102] lpc32xx_mlc: do not use dummy controller config: h8300-randconfig-r003-20200512 (attached as .config) compiler: h8300-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 9cbc57f82b025d7fcdfe329cd916be6a457d81d2 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=h8300 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/mtd/nand/raw/lpc32xx_mlc.c: In function 'lpc32xx_nand_probe': 734 | nfc->controller.ops = &lpc32xx_nand_controller_ops; | ^~~ drivers/mtd/nand/raw/lpc32xx_mlc.c:734:2: note: each undeclared identifier is reported only once for each function it appears in vim +/nfc +734 drivers/mtd/nand/raw/lpc32xx_mlc.c 671 672 /* 673 * Probe for NAND controller 674 */ 675 static int lpc32xx_nand_probe(struct platform_device *pdev) 676 { 677 struct lpc32xx_nand_host *host; 678 struct mtd_info *mtd; 679 struct nand_chip *nand_chip; 680 struct resource *rc; 681 int res; 682 683 /* Allocate memory for the device structure (and zero it) */ 684 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 685 if (!host) 686 return -ENOMEM; 687 688 host->pdev = pdev; 689 690 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); 691 host->io_base = devm_ioremap_resource(&pdev->dev, rc); 692 if (IS_ERR(host->io_base)) 693 return PTR_ERR(host->io_base); 694 695 host->io_base_phy = rc->start; 696 697 nand_chip = &host->nand_chip; 698 mtd = nand_to_mtd(nand_chip); 699 if (pdev->dev.of_node) 700 host->ncfg = lpc32xx_parse_dt(&pdev->dev); 701 if (!host->ncfg) { 702 dev_err(&pdev->dev, 703 "Missing or bad NAND config from device tree\n"); 704 return -ENOENT; 705 } 706 if (host->ncfg->wp_gpio == -EPROBE_DEFER) 707 return -EPROBE_DEFER; 708 if (gpio_is_valid(host->ncfg->wp_gpio) && 709 gpio_request(host->ncfg->wp_gpio, "NAND WP")) { 710 dev_err(&pdev->dev, "GPIO not available\n"); 711 return -EBUSY; 712 } 713 lpc32xx_wp_disable(host); 714 715 host->pdata = dev_get_platdata(&pdev->dev); 716 717 /* link the private data structures */ 718 nand_set_controller_data(nand_chip, host); 719 nand_set_flash_node(nand_chip, pdev->dev.of_node); 720 mtd->dev.parent = &pdev->dev; 721 722 /* Get NAND clock */ 723 host->clk = clk_get(&pdev->dev, NULL); 724 if (IS_ERR(host->clk)) { 725 dev_err(&pdev->dev, "Clock initialization failure\n"); 726 res = -ENOENT; 727 goto free_gpio; 728 } 729 res = clk_prepare_enable(host->clk); 730 if (res) 731 goto put_clk; 732 733 nand_controller_init(&host->controller); 735 736 nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; 737 nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready; 738 nand_chip->legacy.chip_delay = 25; /* us */ 739 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base); 740 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base); 741 742 /* Init NAND controller */ 743 lpc32xx_nand_setup(host); 744 745 platform_set_drvdata(pdev, host); 746 747 /* Initialize function pointers */ 748 nand_chip->ecc.hwctl = lpc32xx_ecc_enable; 749 nand_chip->ecc.read_page_raw = lpc32xx_read_page; 750 nand_chip->ecc.read_page = lpc32xx_read_page; 751 nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; 752 nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel; 753 nand_chip->ecc.write_oob = lpc32xx_write_oob; 754 nand_chip->ecc.read_oob = lpc32xx_read_oob; 755 nand_chip->ecc.strength = 4; 756 nand_chip->ecc.bytes = 10; 757 nand_chip->legacy.waitfunc = lpc32xx_waitfunc; 758 759 nand_chip->options = NAND_NO_SUBPAGE_WRITE; 760 nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 761 nand_chip->bbt_td = &lpc32xx_nand_bbt; 762 nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror; 763 764 if (use_dma) { 765 res = lpc32xx_dma_setup(host); 766 if (res) { 767 res = -EIO; 768 goto unprepare_clk; 769 } 770 } 771 772 /* initially clear interrupt status */ 773 readb(MLC_IRQ_SR(host->io_base)); 774 775 init_completion(&host->comp_nand); 776 init_completion(&host->comp_controller); 777 778 host->irq = platform_get_irq(pdev, 0); 779 if (host->irq < 0) { 780 res = -EINVAL; 781 goto release_dma_chan; 782 } 783 784 if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq, 785 IRQF_TRIGGER_HIGH, DRV_NAME, host)) { 786 dev_err(&pdev->dev, "Error requesting NAND IRQ\n"); 787 res = -ENXIO; 788 goto release_dma_chan; 789 } 790 791 /* 792 * Scan to find existence of the device and get the type of NAND device: 793 * SMALL block or LARGE block. 794 */ 795 res = nand_scan(nand_chip, 1); 796 if (res) 797 goto free_irq; 798 799 mtd->name = DRV_NAME; 800 801 res = mtd_device_register(mtd, host->ncfg->parts, 802 host->ncfg->num_parts); 803 if (res) 804 goto cleanup_nand; 805 806 return 0; 807 808 cleanup_nand: 809 nand_cleanup(nand_chip); 810 free_irq: 811 free_irq(host->irq, host); 812 release_dma_chan: 813 if (use_dma) 814 dma_release_channel(host->dma_chan); 815 unprepare_clk: 816 clk_disable_unprepare(host->clk); 817 put_clk: 818 clk_put(host->clk); 819 free_gpio: 820 lpc32xx_wp_enable(host); 821 gpio_free(host->ncfg->wp_gpio); 822 823 return res; 824 } 825 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org