Hi Lyude, [FYI, it's a private test report for your RFC patch.] [auto build test WARNING on drm-tip/drm-tip] [also build test WARNING on next-20200622] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master drm/drm-next v5.8-rc2] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Lyude-Paul/drm-nouveau-Introduce... base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: arc-allyesconfig (attached as .config) compiler: arc-elf-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): drivers/gpu/drm/nouveau/dispnv50/crc.c: In function 'nv50_crc_atomic_check': 335 | struct nouveau_encoder *outp; | ^~~~ vim +/outp +335 drivers/gpu/drm/nouveau/dispnv50/crc.c 325 326 int nv50_crc_atomic_check(struct nv50_head *head, 327 struct nv50_head_atom *asyh, 328 struct nv50_head_atom *armh) 329 { 330 struct drm_atomic_state *state = asyh->state.state; 331 struct drm_device *dev = head->base.base.dev; 332 struct nv50_atom *atom = nv50_atom(state); 333 struct nv50_disp *disp = nv50_disp(dev); 334 struct drm_encoder *encoder; 336 struct nv50_outp_atom *outp_atom; 337 bool changed = armh->crc.src != asyh->crc.src; 338 339 if (!armh->crc.src && !asyh->crc.src) { 340 asyh->set.crc = false; 341 asyh->clr.crc = false; 342 return 0; 343 } 344 345 /* While we don't care about entry tags, Volta+ hw always needs the 346 * controlling wndw channel programmed to a wndw that's owned by our 347 * head 348 */ 349 if (asyh->crc.src && disp->disp->object.oclass >= GV100_DISP && 350 !(BIT(asyh->crc.wndw) & asyh->wndw.owned)) { 351 if (!asyh->wndw.owned) { 352 /* TODO: once we support flexible channel ownership, 353 * we should write some code here to handle attempting 354 * to "steal" a plane: e.g. take a plane that is 355 * currently not-visible and owned by another head, 356 * and reassign it to this head. If we fail to do so, 357 * we shuld reject the mode outright as CRC capture 358 * then becomes impossible. 359 */ 360 NV_ATOMIC(nouveau_drm(dev), 361 "No available wndws for CRC readback\n"); 362 return -EINVAL; 363 } 364 asyh->crc.wndw = ffs(asyh->wndw.owned) - 1; 365 } 366 367 if (drm_atomic_crtc_needs_modeset(&asyh->state) || changed || 368 armh->crc.wndw != asyh->crc.wndw) { 369 asyh->clr.crc = armh->crc.src && armh->state.active; 370 asyh->set.crc = asyh->crc.src && asyh->state.active; 371 if (changed) 372 asyh->set.or |= armh->or.crc_raster != 373 asyh->or.crc_raster; 374 375 /* 376 * If we're reprogramming our OR, we need to flush the CRC 377 * disable first 378 */ 379 if (asyh->clr.crc) { 380 encoder = nv50_head_atom_get_encoder(armh); 381 outp = nv50_real_outp(encoder); 382 383 list_for_each_entry(outp_atom, &atom->outp, head) { 384 if (outp_atom->encoder == encoder) { 385 if (outp_atom->set.mask) 386 atom->flush_disable = true; 387 break; 388 } 389 } 390 } 391 } else { 392 asyh->set.crc = false; 393 asyh->clr.crc = false; 394 } 395 396 return 0; 397 } 398 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org