tree: https://android.googlesource.com/kernel/goldfish android-3.18 head: e870ebed0381c422cd5fe0fef84693f9f41a3f04 commit: b6ea68099f48ed87fc737797eda1295cd04149b1 [619/620] clockevents/tcb_clksrc: Prevent disabling an already disabled clock config: arm-at91_dt_defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 5.5.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout b6ea68099f48ed87fc737797eda1295cd04149b1 # save the attached .config to linux build tree GCC_VERSION=5.5.0 make.cross ARCH=arm If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp(a)intel.com&gt; Note: the android-goldfish/android-3.18 HEAD 8ebd9d835d6d9ae5225be8a576dd1c7a9c3606eb builds fine. It only hurts bisectibility. All errors (new ones prefixed by >>): drivers/clocksource/tcb_clksrc.c: In function 'tc_mode': if (!clockevent_state_detached(d)) ^ cc1: some warnings being treated as errors vim +/clockevent_state_detached +103 drivers/clocksource/tcb_clksrc.c 93 94 static void tc_mode(enum clock_event_mode m, struct clock_event_device *d) 95 { 96 struct tc_clkevt_device *tcd = to_tc_clkevt(d); 97 void __iomem *regs = tcd->regs; 98 99 if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC 100 || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) { 101 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); 102 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); 104 clk_disable(tcd->clk); 105 } 106 107 switch (m) { 108 109 /* By not making the gentime core emulate periodic mode on top 110 * of oneshot, we get lower overhead and improved accuracy. 111 */ 112 case CLOCK_EVT_MODE_PERIODIC: 113 clk_enable(tcd->clk); 114 115 /* slow clock, count up to RC, then irq and restart */ 116 __raw_writel(timer_clock 117 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, 118 regs + ATMEL_TC_REG(2, CMR)); 119 __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); 120 121 /* Enable clock and interrupts on RC compare */ 122 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 123 124 /* go go gadget! */ 125 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, 126 regs + ATMEL_TC_REG(2, CCR)); 127 break; 128 129 case CLOCK_EVT_MODE_ONESHOT: 130 clk_enable(tcd->clk); 131 132 /* slow clock, count up to RC, then irq and stop */ 133 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP 134 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, 135 regs + ATMEL_TC_REG(2, CMR)); 136 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 137 138 /* set_next_event() configures and starts the timer */ 139 break; 140 141 default: 142 break; 143 } 144 } 145 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org