tree: https://github.com/Freescale/linux-fslc pr/517 head: fdd91487f014d6f66a7db03f135056ada3552f27 commit: fef46455683f097673cd4eef816b185baf141dce [12427/22154] MLK-24206-3 usb: dwc3: core: add fladj setting if SOFITPSYNC used config: arc-buildonly-randconfig-r005-20220110 (https://download.01.org/0day-ci/archive/20220111/202201110535.9nsxOmxE-lk...) compiler: arc-elf-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/Freescale/linux-fslc/commit/fef46455683f097673cd4eef81... git remote add freescale-fslc https://github.com/Freescale/linux-fslc git fetch --no-tags freescale-fslc pr/517 git checkout fef46455683f097673cd4eef816b185baf141dce # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash drivers/usb/dwc3/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/usb/dwc3/core.c: In function 'dwc3_frame_length_adjustment': 339 | temp = 125000L * 1000000000L; | ^ vim +339 drivers/usb/dwc3/core.c 304 305 /* 306 * dwc3_frame_length_adjustment - Adjusts frame length if required 307 * @dwc3: Pointer to our controller context structure 308 */ 309 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 310 { 311 u32 reg; 312 u32 dft; 313 314 /* 315 * if GCTL.SOFITPSYNC is set to '1': 316 * FLADJ_REF_CLK_FLADJ= 317 * ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * 318 * ref_clk_period 319 * where 320 * - the ref_clk_period_integer is the integer value of 321 * the ref_clk period got by truncating the decimal (fractional) 322 * value that is programmed in the GUCTL.REF_CLK_PERIOD field. 323 * - the ref_clk_period is the ref_clk period including the fractional 324 * value. 325 */ 326 if (dwc->soft_itp_sync_quirk) { 327 u32 ref_clk_hz, ref_clk_period_integer; 328 u64 temp; 329 330 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 331 ref_clk_hz = clk_get_rate(dwc->clks[0].clk); 332 if (ref_clk_hz == 0) { 333 dev_err(dwc->dev, "ref clk is 0, can't set fladj\n"); 334 return; 335 } 336 337 /* nano seconds the period of ref_clk */ 338 ref_clk_period_integer = 1000000000 / ref_clk_hz; 340 temp = temp / ref_clk_hz; 341 temp = temp / ref_clk_period_integer; 342 temp = temp - 125000; 343 temp = temp << GFLADJ_REFCLK_FLADJ_SHIFT; 344 reg &= ~GFLADJ_REFCLK_FLADJ_MASK; 345 reg |= temp; 346 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 347 348 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 349 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 350 reg |= ref_clk_period_integer << DWC3_GUCTL_REFCLKPER_SHIFT; 351 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 352 } 353 354 if (dwc->revision < DWC3_REVISION_250A) 355 return; 356 357 if (dwc->fladj == 0) 358 return; 359 360 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 361 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 362 if (dft != dwc->fladj) { 363 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 364 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 365 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 366 } 367 } 368 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org