tree: https://gitlab.freedesktop.org/agd5f/linux.git drm-next head: 412562f576272dbb614fa937b6a80819a6bbb233 commit: 412562f576272dbb614fa937b6a80819a6bbb233 [137/137] drm/amdgpu: Add graphics cache rinse packet for sdma 5.0 config: x86_64-randconfig-m001-20210421 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; smatch warnings: drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:457 sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting vim +457 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 439 440 /** 441 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 442 * 443 * @ring: amdgpu ring pointer 444 * @job: job to retrieve vmid from 445 * @ib: IB object to schedule 446 * 447 * flush the IB by graphics cache rinse. 448 */ 449 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 450 { 451 uint32_t gcr_cntl = 452 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 453 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 454 SDMA_GCR_GLI_INV(1); 455 456 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 458 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 459 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 460 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 461 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 462 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 463 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 464 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 465 } 466 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org