Hi Vishal, Thank you for the patch! Yet something to improve: [auto build test ERROR on linuxtv-media/master] [also build test ERROR on robh/for-next v5.8-rc1 next-20200618] [cannot apply to xlnx/master] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Vishal-Sagar/Add-support-for-Xil... base: git://linuxtv.org/media_tree.git master config: arc-allyesconfig (attached as .config) compiler: arc-elf-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All error/warnings (new ones prefixed by >>): vim +/irqreturn_t +1113 drivers/media/platform/xilinx/xilinx-sdirxss.c 1103 1104 /** 1105 * xsdirxss_irq_handler - Interrupt handler for SDI Rx 1106 * @irq: IRQ number 1107 * @dev_id: Pointer to device state 1108 * 1109 * The SDI Rx interrupts are cleared by writing 1 to corresponding bit. 1110 * 1111 * Return: IRQ_HANDLED after handling interrupts 1112 */ 1114 { 1115 struct xsdirxss_state *state = (struct xsdirxss_state *)dev_id; 1116 struct device *dev = state->dev; 1117 u32 status; 1118 1119 status = xsdirxss_read(state, XSDIRX_ISR_REG); 1120 xsdirxss_write(state, XSDIRX_ISR_REG, status); 1121 dev_dbg(dev, "interrupt status = 0x%08x\n", status); 1122 1123 if (!status) 1125 1126 if (status & XSDIRX_INTR_VIDLOCK_MASK || 1127 status & XSDIRX_INTR_VIDUNLOCK_MASK) { 1128 u32 val1, val2; 1129 struct v4l2_event event = { 0 }; 1130 unsigned long flags; 1131 1132 dev_dbg(dev, "video lock/unlock interrupt\n"); 1133 1134 spin_lock_irqsave(&state->slock, flags); 1135 xsdirx_streamflow_control(state, false); 1136 1137 val1 = xsdirxss_read(state, XSDIRX_MODE_DET_STAT_REG); 1138 val2 = xsdirxss_read(state, XSDIRX_TS_DET_STAT_REG); 1139 1140 if ((val1 & XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK) && 1141 (val2 & XSDIRX_TS_DET_STAT_LOCKED_MASK)) { 1142 u32 mask = XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK | 1143 XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK; 1144 1145 dev_dbg(dev, "video lock interrupt\n"); 1146 1147 xsdirxss_set(state, XSDIRX_RST_CTRL_REG, mask); 1148 xsdirxss_clr(state, XSDIRX_RST_CTRL_REG, mask); 1149 1150 val1 = xsdirxss_read(state, XSDIRX_ST352_VALID_REG); 1151 val2 = xsdirxss_read(state, XSDIRX_ST352_DS1_REG); 1152 1153 dev_dbg(dev, "valid st352 mask = 0x%08x\n", val1); 1154 dev_dbg(dev, "st352 payload = 0x%08x\n", val2); 1155 1156 if (!xsdirx_get_stream_properties(state)) { 1157 state->vidlocked = true; 1158 xsdirxss_set_gtclk(state); 1159 } else { 1160 dev_err(dev, "Unable to get stream properties!\n"); 1161 state->vidlocked = false; 1162 } 1163 } else { 1164 dev_dbg(dev, "video unlock interrupt\n"); 1165 state->vidlocked = false; 1166 } 1167 spin_unlock_irqrestore(&state->slock, flags); 1168 1169 event.type = V4L2_EVENT_SOURCE_CHANGE; 1170 event.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION; 1171 v4l2_subdev_notify_event(&state->subdev, &event); 1172 } 1173 1174 if (status & (XSDIRX_INTR_UNDERFLOW_MASK | XSDIRX_INTR_OVERFLOW_MASK)) { 1175 struct v4l2_event event = { 0 }; 1176 1177 dev_dbg(dev, "Video in to AXI4 Stream core under/overflow interrupt\n"); 1178 1179 event.type = V4L2_EVENT_XILINX_SDIRX_UND_OVR_FLOW; 1180 if (status & XSDIRX_INTR_UNDERFLOW_MASK) 1181 event.u.data[0] = XILINX_SDIRX_UNDERFLOW_EVENT; 1182 if (status & XSDIRX_INTR_OVERFLOW_MASK) 1183 event.u.data[0] = XILINX_SDIRX_OVERFLOW_EVENT; 1184 1185 v4l2_subdev_notify_event(&state->subdev, &event); 1186 } 1188 } 1189 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org