tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/urgent head: e16a1731f2dcd4cd58ef3217dca4edde2bddd24f commit: cf6529bb112e1e5fe946781c07eac8a8944c538a [4/11] perf/x86/intel: Add Comet Lake CPU support config: x86_64-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.4.0-13) 7.4.0 reproduce: git checkout cf6529bb112e1e5fe946781c07eac8a8944c538a # save the attached .config to linux build tree make ARCH=x86_64 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): arch/x86/events/intel/core.c: In function 'intel_pmu_init': case INTEL_FAM6_COMETLAKE_L: ^~~~~~~~~~~~~~~~~~~~~~ INTEL_FAM6_ICELAKE_L arch/x86/events/intel/core.c:4986:7: note: each undeclared identifier is reported only once for each function it appears in case INTEL_FAM6_COMETLAKE: ^~~~~~~~~~~~~~~~~~~~ INTEL_FAM6_COMETLAKE_L vim +4986 arch/x86/events/intel/core.c 4512 4513 __init int intel_pmu_init(void) 4514 { 4515 struct attribute **extra_skl_attr = &empty_attrs; 4516 struct attribute **extra_attr = &empty_attrs; 4517 struct attribute **td_attr = &empty_attrs; 4518 struct attribute **mem_attr = &empty_attrs; 4519 struct attribute **tsx_attr = &empty_attrs; 4520 union cpuid10_edx edx; 4521 union cpuid10_eax eax; 4522 union cpuid10_ebx ebx; 4523 struct event_constraint *c; 4524 unsigned int unused; 4525 struct extra_reg *er; 4526 bool pmem = false; 4527 int version, i; 4528 char *name; 4529 4530 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4531 switch (boot_cpu_data.x86) { 4532 case 0x6: 4533 return p6_pmu_init(); 4534 case 0xb: 4535 return knc_pmu_init(); 4536 case 0xf: 4537 return p4_pmu_init(); 4538 } 4539 return -ENODEV; 4540 } 4541 4542 /* 4543 * Check whether the Architectural PerfMon supports 4544 * Branch Misses Retired hw_event or not. 4545 */ 4546 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4547 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4548 return -ENODEV; 4549 4550 version = eax.split.version_id; 4551 if (version < 2) 4552 x86_pmu = core_pmu; 4553 else 4554 x86_pmu = intel_pmu; 4555 4556 x86_pmu.version = version; 4557 x86_pmu.num_counters = eax.split.num_counters; 4558 x86_pmu.cntval_bits = eax.split.bit_width; 4559 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4560 4561 x86_pmu.events_maskl = ebx.full; 4562 x86_pmu.events_mask_len = eax.split.mask_length; 4563 4564 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4565 4566 /* 4567 * Quirk: v2 perfmon does not report fixed-purpose events, so 4568 * assume at least 3 events, when not running in a hypervisor: 4569 */ 4570 if (version > 1) { 4571 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4572 4573 x86_pmu.num_counters_fixed = 4574 max((int)edx.split.num_counters_fixed, assume); 4575 } 4576 4577 if (version >= 4) 4578 x86_pmu.counter_freezing = !disable_counter_freezing; 4579 4580 if (boot_cpu_has(X86_FEATURE_PDCM)) { 4581 u64 capabilities; 4582 4583 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4584 x86_pmu.intel_cap.capabilities = capabilities; 4585 } 4586 4587 intel_ds_init(); 4588 4589 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4590 4591 /* 4592 * Install the hw-cache-events table: 4593 */ 4594 switch (boot_cpu_data.x86_model) { 4595 case INTEL_FAM6_CORE_YONAH: 4596 pr_cont("Core events, "); 4597 name = "core"; 4598 break; 4599 4600 case INTEL_FAM6_CORE2_MEROM: 4601 x86_add_quirk(intel_clovertown_quirk); 4602 /* fall through */ 4603 4604 case INTEL_FAM6_CORE2_MEROM_L: 4605 case INTEL_FAM6_CORE2_PENRYN: 4606 case INTEL_FAM6_CORE2_DUNNINGTON: 4607 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 4608 sizeof(hw_cache_event_ids)); 4609 4610 intel_pmu_lbr_init_core(); 4611 4612 x86_pmu.event_constraints = intel_core2_event_constraints; 4613 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 4614 pr_cont("Core2 events, "); 4615 name = "core2"; 4616 break; 4617 4618 case INTEL_FAM6_NEHALEM: 4619 case INTEL_FAM6_NEHALEM_EP: 4620 case INTEL_FAM6_NEHALEM_EX: 4621 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 4622 sizeof(hw_cache_event_ids)); 4623 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4624 sizeof(hw_cache_extra_regs)); 4625 4626 intel_pmu_lbr_init_nhm(); 4627 4628 x86_pmu.event_constraints = intel_nehalem_event_constraints; 4629 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 4630 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4631 x86_pmu.extra_regs = intel_nehalem_extra_regs; 4632 x86_pmu.limit_period = nhm_limit_period; 4633 4634 mem_attr = nhm_mem_events_attrs; 4635 4636 /* UOPS_ISSUED.STALLED_CYCLES */ 4637 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4638 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4639 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4640 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4641 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4642 4643 intel_pmu_pebs_data_source_nhm(); 4644 x86_add_quirk(intel_nehalem_quirk); 4645 x86_pmu.pebs_no_tlb = 1; 4646 extra_attr = nhm_format_attr; 4647 4648 pr_cont("Nehalem events, "); 4649 name = "nehalem"; 4650 break; 4651 4652 case INTEL_FAM6_ATOM_BONNELL: 4653 case INTEL_FAM6_ATOM_BONNELL_MID: 4654 case INTEL_FAM6_ATOM_SALTWELL: 4655 case INTEL_FAM6_ATOM_SALTWELL_MID: 4656 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 4657 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 4658 sizeof(hw_cache_event_ids)); 4659 4660 intel_pmu_lbr_init_atom(); 4661 4662 x86_pmu.event_constraints = intel_gen_event_constraints; 4663 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 4664 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 4665 pr_cont("Atom events, "); 4666 name = "bonnell"; 4667 break; 4668 4669 case INTEL_FAM6_ATOM_SILVERMONT: 4670 case INTEL_FAM6_ATOM_SILVERMONT_D: 4671 case INTEL_FAM6_ATOM_SILVERMONT_MID: 4672 case INTEL_FAM6_ATOM_AIRMONT: 4673 case INTEL_FAM6_ATOM_AIRMONT_MID: 4674 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4675 sizeof(hw_cache_event_ids)); 4676 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4677 sizeof(hw_cache_extra_regs)); 4678 4679 intel_pmu_lbr_init_slm(); 4680 4681 x86_pmu.event_constraints = intel_slm_event_constraints; 4682 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4683 x86_pmu.extra_regs = intel_slm_extra_regs; 4684 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4685 td_attr = slm_events_attrs; 4686 extra_attr = slm_format_attr; 4687 pr_cont("Silvermont events, "); 4688 name = "silvermont"; 4689 break; 4690 4691 case INTEL_FAM6_ATOM_GOLDMONT: 4692 case INTEL_FAM6_ATOM_GOLDMONT_D: 4693 x86_add_quirk(intel_counter_freezing_quirk); 4694 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 4695 sizeof(hw_cache_event_ids)); 4696 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 4697 sizeof(hw_cache_extra_regs)); 4698 4699 intel_pmu_lbr_init_skl(); 4700 4701 x86_pmu.event_constraints = intel_slm_event_constraints; 4702 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 4703 x86_pmu.extra_regs = intel_glm_extra_regs; 4704 /* 4705 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4706 * for precise cycles. 4707 * :pp is identical to :ppp 4708 */ 4709 x86_pmu.pebs_aliases = NULL; 4710 x86_pmu.pebs_prec_dist = true; 4711 x86_pmu.lbr_pt_coexist = true; 4712 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4713 td_attr = glm_events_attrs; 4714 extra_attr = slm_format_attr; 4715 pr_cont("Goldmont events, "); 4716 name = "goldmont"; 4717 break; 4718 4719 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4720 x86_add_quirk(intel_counter_freezing_quirk); 4721 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4722 sizeof(hw_cache_event_ids)); 4723 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4724 sizeof(hw_cache_extra_regs)); 4725 4726 intel_pmu_lbr_init_skl(); 4727 4728 x86_pmu.event_constraints = intel_slm_event_constraints; 4729 x86_pmu.extra_regs = intel_glm_extra_regs; 4730 /* 4731 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4732 * for precise cycles. 4733 */ 4734 x86_pmu.pebs_aliases = NULL; 4735 x86_pmu.pebs_prec_dist = true; 4736 x86_pmu.lbr_pt_coexist = true; 4737 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4738 x86_pmu.flags |= PMU_FL_PEBS_ALL; 4739 x86_pmu.get_event_constraints = glp_get_event_constraints; 4740 td_attr = glm_events_attrs; 4741 /* Goldmont Plus has 4-wide pipeline */ 4742 event_attr_td_total_slots_scale_glm.event_str = "4"; 4743 extra_attr = slm_format_attr; 4744 pr_cont("Goldmont plus events, "); 4745 name = "goldmont_plus"; 4746 break; 4747 4748 case INTEL_FAM6_ATOM_TREMONT_D: 4749 x86_pmu.late_ack = true; 4750 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4751 sizeof(hw_cache_event_ids)); 4752 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 4753 sizeof(hw_cache_extra_regs)); 4754 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 4755 4756 intel_pmu_lbr_init_skl(); 4757 4758 x86_pmu.event_constraints = intel_slm_event_constraints; 4759 x86_pmu.extra_regs = intel_tnt_extra_regs; 4760 /* 4761 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4762 * for precise cycles. 4763 */ 4764 x86_pmu.pebs_aliases = NULL; 4765 x86_pmu.pebs_prec_dist = true; 4766 x86_pmu.lbr_pt_coexist = true; 4767 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4768 x86_pmu.get_event_constraints = tnt_get_event_constraints; 4769 extra_attr = slm_format_attr; 4770 pr_cont("Tremont events, "); 4771 name = "Tremont"; 4772 break; 4773 4774 case INTEL_FAM6_WESTMERE: 4775 case INTEL_FAM6_WESTMERE_EP: 4776 case INTEL_FAM6_WESTMERE_EX: 4777 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4778 sizeof(hw_cache_event_ids)); 4779 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4780 sizeof(hw_cache_extra_regs)); 4781 4782 intel_pmu_lbr_init_nhm(); 4783 4784 x86_pmu.event_constraints = intel_westmere_event_constraints; 4785 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4786 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4787 x86_pmu.extra_regs = intel_westmere_extra_regs; 4788 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4789 4790 mem_attr = nhm_mem_events_attrs; 4791 4792 /* UOPS_ISSUED.STALLED_CYCLES */ 4793 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4794 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4795 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4796 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4797 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4798 4799 intel_pmu_pebs_data_source_nhm(); 4800 extra_attr = nhm_format_attr; 4801 pr_cont("Westmere events, "); 4802 name = "westmere"; 4803 break; 4804 4805 case INTEL_FAM6_SANDYBRIDGE: 4806 case INTEL_FAM6_SANDYBRIDGE_X: 4807 x86_add_quirk(intel_sandybridge_quirk); 4808 x86_add_quirk(intel_ht_bug); 4809 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4810 sizeof(hw_cache_event_ids)); 4811 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4812 sizeof(hw_cache_extra_regs)); 4813 4814 intel_pmu_lbr_init_snb(); 4815 4816 x86_pmu.event_constraints = intel_snb_event_constraints; 4817 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4818 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4819 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4820 x86_pmu.extra_regs = intel_snbep_extra_regs; 4821 else 4822 x86_pmu.extra_regs = intel_snb_extra_regs; 4823 4824 4825 /* all extra regs are per-cpu when HT is on */ 4826 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4827 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4828 4829 td_attr = snb_events_attrs; 4830 mem_attr = snb_mem_events_attrs; 4831 4832 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4833 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4834 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4835 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4836 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4837 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4838 4839 extra_attr = nhm_format_attr; 4840 4841 pr_cont("SandyBridge events, "); 4842 name = "sandybridge"; 4843 break; 4844 4845 case INTEL_FAM6_IVYBRIDGE: 4846 case INTEL_FAM6_IVYBRIDGE_X: 4847 x86_add_quirk(intel_ht_bug); 4848 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4849 sizeof(hw_cache_event_ids)); 4850 /* dTLB-load-misses on IVB is different than SNB */ 4851 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4852 4853 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4854 sizeof(hw_cache_extra_regs)); 4855 4856 intel_pmu_lbr_init_snb(); 4857 4858 x86_pmu.event_constraints = intel_ivb_event_constraints; 4859 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4860 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4861 x86_pmu.pebs_prec_dist = true; 4862 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4863 x86_pmu.extra_regs = intel_snbep_extra_regs; 4864 else 4865 x86_pmu.extra_regs = intel_snb_extra_regs; 4866 /* all extra regs are per-cpu when HT is on */ 4867 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4868 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4869 4870 td_attr = snb_events_attrs; 4871 mem_attr = snb_mem_events_attrs; 4872 4873 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4874 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4875 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4876 4877 extra_attr = nhm_format_attr; 4878 4879 pr_cont("IvyBridge events, "); 4880 name = "ivybridge"; 4881 break; 4882 4883 4884 case INTEL_FAM6_HASWELL: 4885 case INTEL_FAM6_HASWELL_X: 4886 case INTEL_FAM6_HASWELL_L: 4887 case INTEL_FAM6_HASWELL_G: 4888 x86_add_quirk(intel_ht_bug); 4889 x86_add_quirk(intel_pebs_isolation_quirk); 4890 x86_pmu.late_ack = true; 4891 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4892 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4893 4894 intel_pmu_lbr_init_hsw(); 4895 4896 x86_pmu.event_constraints = intel_hsw_event_constraints; 4897 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4898 x86_pmu.extra_regs = intel_snbep_extra_regs; 4899 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4900 x86_pmu.pebs_prec_dist = true; 4901 /* all extra regs are per-cpu when HT is on */ 4902 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4903 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4904 4905 x86_pmu.hw_config = hsw_hw_config; 4906 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4907 x86_pmu.lbr_double_abort = true; 4908 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4909 hsw_format_attr : nhm_format_attr; 4910 td_attr = hsw_events_attrs; 4911 mem_attr = hsw_mem_events_attrs; 4912 tsx_attr = hsw_tsx_events_attrs; 4913 pr_cont("Haswell events, "); 4914 name = "haswell"; 4915 break; 4916 4917 case INTEL_FAM6_BROADWELL: 4918 case INTEL_FAM6_BROADWELL_D: 4919 case INTEL_FAM6_BROADWELL_G: 4920 case INTEL_FAM6_BROADWELL_X: 4921 x86_add_quirk(intel_pebs_isolation_quirk); 4922 x86_pmu.late_ack = true; 4923 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4924 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4925 4926 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4927 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4928 BDW_L3_MISS|HSW_SNOOP_DRAM; 4929 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4930 HSW_SNOOP_DRAM; 4931 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4932 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4933 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4934 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4935 4936 intel_pmu_lbr_init_hsw(); 4937 4938 x86_pmu.event_constraints = intel_bdw_event_constraints; 4939 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4940 x86_pmu.extra_regs = intel_snbep_extra_regs; 4941 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4942 x86_pmu.pebs_prec_dist = true; 4943 /* all extra regs are per-cpu when HT is on */ 4944 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4945 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4946 4947 x86_pmu.hw_config = hsw_hw_config; 4948 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4949 x86_pmu.limit_period = bdw_limit_period; 4950 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4951 hsw_format_attr : nhm_format_attr; 4952 td_attr = hsw_events_attrs; 4953 mem_attr = hsw_mem_events_attrs; 4954 tsx_attr = hsw_tsx_events_attrs; 4955 pr_cont("Broadwell events, "); 4956 name = "broadwell"; 4957 break; 4958 4959 case INTEL_FAM6_XEON_PHI_KNL: 4960 case INTEL_FAM6_XEON_PHI_KNM: 4961 memcpy(hw_cache_event_ids, 4962 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4963 memcpy(hw_cache_extra_regs, 4964 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4965 intel_pmu_lbr_init_knl(); 4966 4967 x86_pmu.event_constraints = intel_slm_event_constraints; 4968 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4969 x86_pmu.extra_regs = intel_knl_extra_regs; 4970 4971 /* all extra regs are per-cpu when HT is on */ 4972 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4973 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4974 extra_attr = slm_format_attr; 4975 pr_cont("Knights Landing/Mill events, "); 4976 name = "knights-landing"; 4977 break; 4978 4979 case INTEL_FAM6_SKYLAKE_X: 4980 pmem = true; 4981 /* fall through */ 4982 case INTEL_FAM6_SKYLAKE_L: 4983 case INTEL_FAM6_SKYLAKE: 4984 case INTEL_FAM6_KABYLAKE_L: 4985 case INTEL_FAM6_KABYLAKE: 4988 x86_add_quirk(intel_pebs_isolation_quirk); 4989 x86_pmu.late_ack = true; 4990 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4991 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4992 intel_pmu_lbr_init_skl(); 4993 4994 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4995 event_attr_td_recovery_bubbles.event_str_noht = 4996 "event=0xd,umask=0x1,cmask=1"; 4997 event_attr_td_recovery_bubbles.event_str_ht = 4998 "event=0xd,umask=0x1,cmask=1,any=1"; 4999 5000 x86_pmu.event_constraints = intel_skl_event_constraints; 5001 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 5002 x86_pmu.extra_regs = intel_skl_extra_regs; 5003 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 5004 x86_pmu.pebs_prec_dist = true; 5005 /* all extra regs are per-cpu when HT is on */ 5006 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5007 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5008 5009 x86_pmu.hw_config = hsw_hw_config; 5010 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5011 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5012 hsw_format_attr : nhm_format_attr; 5013 extra_skl_attr = skl_format_attr; 5014 td_attr = hsw_events_attrs; 5015 mem_attr = hsw_mem_events_attrs; 5016 tsx_attr = hsw_tsx_events_attrs; 5017 intel_pmu_pebs_data_source_skl(pmem); 5018 5019 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 5020 x86_pmu.flags |= PMU_FL_TFA; 5021 x86_pmu.get_event_constraints = tfa_get_event_constraints; 5022 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 5023 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 5024 } 5025 5026 pr_cont("Skylake events, "); 5027 name = "skylake"; 5028 break; 5029 5030 case INTEL_FAM6_ICELAKE_X: 5031 case INTEL_FAM6_ICELAKE_D: 5032 pmem = true; 5033 /* fall through */ 5034 case INTEL_FAM6_ICELAKE_L: 5035 case INTEL_FAM6_ICELAKE: 5036 x86_pmu.late_ack = true; 5037 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5038 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5039 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5040 intel_pmu_lbr_init_skl(); 5041 5042 x86_pmu.event_constraints = intel_icl_event_constraints; 5043 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 5044 x86_pmu.extra_regs = intel_icl_extra_regs; 5045 x86_pmu.pebs_aliases = NULL; 5046 x86_pmu.pebs_prec_dist = true; 5047 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5048 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5049 5050 x86_pmu.hw_config = hsw_hw_config; 5051 x86_pmu.get_event_constraints = icl_get_event_constraints; 5052 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5053 hsw_format_attr : nhm_format_attr; 5054 extra_skl_attr = skl_format_attr; 5055 mem_attr = icl_events_attrs; 5056 tsx_attr = icl_tsx_events_attrs; 5057 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02); 5058 x86_pmu.lbr_pt_coexist = true; 5059 intel_pmu_pebs_data_source_skl(pmem); 5060 pr_cont("Icelake events, "); 5061 name = "icelake"; 5062 break; 5063 5064 default: 5065 switch (x86_pmu.version) { 5066 case 1: 5067 x86_pmu.event_constraints = intel_v1_event_constraints; 5068 pr_cont("generic architected perfmon v1, "); 5069 name = "generic_arch_v1"; 5070 break; 5071 default: 5072 /* 5073 * default constraints for v2 and up 5074 */ 5075 x86_pmu.event_constraints = intel_gen_event_constraints; 5076 pr_cont("generic architected perfmon, "); 5077 name = "generic_arch_v2+"; 5078 break; 5079 } 5080 } 5081 5082 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 5083 5084 5085 group_events_td.attrs = td_attr; 5086 group_events_mem.attrs = mem_attr; 5087 group_events_tsx.attrs = tsx_attr; 5088 group_format_extra.attrs = extra_attr; 5089 group_format_extra_skl.attrs = extra_skl_attr; 5090 5091 x86_pmu.attr_update = attr_update; 5092 5093 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5094 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5095 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5096 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5097 } 5098 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5099 5100 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5101 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5102 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5103 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5104 } 5105 5106 x86_pmu.intel_ctrl |= 5107 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5108 5109 if (x86_pmu.event_constraints) { 5110 /* 5111 * event on fixed counter2 (REF_CYCLES) only works on this 5112 * counter, so do not extend mask to generic counters 5113 */ 5114 for_each_event_constraint(c, x86_pmu.event_constraints) { 5115 if (c->cmask == FIXED_EVENT_FLAGS 5116 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5117 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5118 } 5119 c->idxmsk64 &= 5120 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5121 c->weight = hweight64(c->idxmsk64); 5122 } 5123 } 5124 5125 /* 5126 * Access LBR MSR may cause #GP under certain circumstances. 5127 * E.g. KVM doesn't support LBR MSR 5128 * Check all LBT MSR here. 5129 * Disable LBR access if any LBR MSRs can not be accessed. 5130 */ 5131 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5132 x86_pmu.lbr_nr = 0; 5133 for (i = 0; i < x86_pmu.lbr_nr; i++) { 5134 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5135 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5136 x86_pmu.lbr_nr = 0; 5137 } 5138 5139 if (x86_pmu.lbr_nr) 5140 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5141 5142 /* 5143 * Access extra MSR may cause #GP under certain circumstances. 5144 * E.g. KVM doesn't support offcore event 5145 * Check all extra_regs here. 5146 */ 5147 if (x86_pmu.extra_regs) { 5148 for (er = x86_pmu.extra_regs; er->msr; er++) { 5149 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5150 /* Disable LBR select mapping */ 5151 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5152 x86_pmu.lbr_sel_map = NULL; 5153 } 5154 } 5155 5156 /* Support full width counters using alternative MSR range */ 5157 if (x86_pmu.intel_cap.full_width_write) { 5158 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5159 x86_pmu.perfctr = MSR_IA32_PMC0; 5160 pr_cont("full-width counters, "); 5161 } 5162 5163 /* 5164 * For arch perfmon 4 use counter freezing to avoid 5165 * several MSR accesses in the PMI. 5166 */ 5167 if (x86_pmu.counter_freezing) 5168 x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 5169 5170 return 0; 5171 } 5172 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation