[linux-next:master 5074/7806] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:42:20: error: no previous prototype for 'to_dal_irq_source_dcn201'
10 p.m.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 8006b911c90a4ec09958447d24c8a4c3538f5723
commit: 3f68c01be9a2227de1e190317fe34a6fb835a094 [5074/7806] drm/amd/display: add
cyan_skillfish display support
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commi...
git remote add linux-next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout 3f68c01be9a2227de1e190317fe34a6fb835a094
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
>
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:42:20: error: no
previous prototype for 'to_dal_irq_source_dcn201' [-Werror=missing-prototypes]
42 | enum dc_irq_source to_dal_irq_source_dcn201(
| ^~~~~~~~~~~~~~~~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:142:43: error:
'dmub_outbox_irq_info_funcs' defined but not used [-Werror=unused-const-variable=]
142 | static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:35:
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: error:
'UVD0_BASE' defined but not used [-Werror=unused-const-variable=]
129 |
static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0
} },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: error:
'UMC0_BASE' defined but not used [-Werror=unused-const-variable=]
123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0,
0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: error:
'THM_BASE' defined but not used [-Werror=unused-const-variable=]
117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0
} },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: error:
'SMUIO_BASE' defined but not used [-Werror=unused-const-variable=]
111
| static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0,
0 } },
| ^~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: error:
'OSSSYS_BASE' defined but not used [-Werror=unused-const-variable=]
105
| static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
| ^~~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: error:
'NBIO_BASE' defined but not used [-Werror=unused-const-variable=]
99 |
static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014,
0x00000D20, 0x00010400, 0 } },
| ^~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: error:
'MP1_BASE' defined but not used [-Werror=unused-const-variable=]
93 |
static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: error:
'MP0_BASE' defined but not used [-Werror=unused-const-variable=]
87 |
static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: error:
'MMHUB_BASE' defined but not used [-Werror=unused-const-variable=]
81
| static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
| ^~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: error:
'HDP_BASE' defined but not used [-Werror=unused-const-variable=]
75 |
static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: error:
'GC_BASE' defined but not used [-Werror=unused-const-variable=]
69 |
static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 }
},
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: error:
'FUSE_BASE' defined but not used [-Werror=unused-const-variable=]
63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0,
0 } },
| ^~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: error:
'DMU_BASE' defined but not used [-Werror=unused-const-variable=]
57 |
static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0,
0x000034C0, 0x00009000, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: error:
'DF_BASE' defined but not used [-Werror=unused-const-variable=]
51 |
static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: error:
'CLK_BASE' defined but not used [-Werror=unused-const-variable=]
45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0
} },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: error:
'ATHUB_BASE' defined but not used [-Werror=unused-const-variable=]
39
| static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
| ^~~~~~~~~~
cc1: all warnings being treated as errors
--
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:79:6: error: no
previous prototype for 'dcn201_update_clocks_vbios' [-Werror=missing-prototypes]
79 | void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c: In function
'dcn201_update_clocks':
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:134:7: error:
variable 'enter_display_off' set but not used [-Werror=unused-but-set-variable]
134 | bool enter_display_off = false;
| ^~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:38:
At top level:
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: error:
'UVD0_BASE' defined but not used [-Werror=unused-const-variable=]
129 |
static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0
} },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: error:
'UMC0_BASE' defined but not used [-Werror=unused-const-variable=]
123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0,
0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: error:
'THM_BASE' defined but not used [-Werror=unused-const-variable=]
117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0
} },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: error:
'SMUIO_BASE' defined but not used [-Werror=unused-const-variable=]
111
| static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0,
0 } },
| ^~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: error:
'OSSSYS_BASE' defined but not used [-Werror=unused-const-variable=]
105
| static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
| ^~~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: error:
'NBIO_BASE' defined but not used [-Werror=unused-const-variable=]
99 |
static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014,
0x00000D20, 0x00010400, 0 } },
| ^~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: error:
'MP1_BASE' defined but not used [-Werror=unused-const-variable=]
93 |
static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: error:
'MP0_BASE' defined but not used [-Werror=unused-const-variable=]
87 |
static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: error:
'MMHUB_BASE' defined but not used [-Werror=unused-const-variable=]
81
| static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
| ^~~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: error:
'HDP_BASE' defined but not used [-Werror=unused-const-variable=]
75 |
static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: error:
'GC_BASE' defined but not used [-Werror=unused-const-variable=]
69 |
static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 }
},
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: error:
'FUSE_BASE' defined but not used [-Werror=unused-const-variable=]
63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0,
0 } },
| ^~~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: error:
'DMU_BASE' defined but not used [-Werror=unused-const-variable=]
57 |
static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0,
0x000034C0, 0x00009000, 0 } },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: error:
'DF_BASE' defined but not used [-Werror=unused-const-variable=]
51 |
static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: error:
'CLK_BASE' defined but not used [-Werror=unused-const-variable=]
45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0
} },
| ^~~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: error:
'ATHUB_BASE' defined but not used [-Werror=unused-const-variable=]
39
| static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
| ^~~~~~~~~~
cc1: all warnings being treated as errors
--
>
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_init.c:127:6: error: no previous
prototype for 'dcn201_hw_sequencer_construct' [-Werror=missing-prototypes]
127 | void dcn201_hw_sequencer_construct(struct dc *dc)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
--
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64:
>
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16515:111: error:
initialized field overwritten [-Werror=override-init]
16515 | #define
DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
0x1f
|
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of
macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of
macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:2: note: in
expansion of macro 'DCN_AUX_MASK_SH_LIST'
365 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16515:111: note:
(near initialization for 'aux_shift.AUX_SW_AUTOINCREMENT_DISABLE')
16515 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
0x1f
|
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of
macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of
macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:2: note: in
expansion of macro 'DCN_AUX_MASK_SH_LIST'
365 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111:
error: initialized field overwritten [-Werror=override-init]
16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
0x80000000L
|
^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of
macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of
macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:2: note: in
expansion of macro 'DCN_AUX_MASK_SH_LIST'
369 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111: note:
(near initialization for 'aux_mask.AUX_SW_AUTOINCREMENT_DISABLE')
16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
0x80000000L
|
^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:16: note: in expansion of
macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
213 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:2: note: in expansion of
macro 'AUX_SF'
203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:2: note: in
expansion of macro 'DCN_AUX_MASK_SH_LIST'
369 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111:
error: initialized field overwritten [-Werror=override-init]
17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
0x0
|
^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in
expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in
expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:3: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111: note:
(near initialization for 'le_shift.TMDS_CTL0')
17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT
0x0
|
^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in
expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in
expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:3: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111:
error: initialized field overwritten [-Werror=override-init]
17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK
0x00000001L
|
^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in
expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in
expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:3: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111: note:
(near initialization for 'le_mask.TMDS_CTL0')
17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK
0x00000001L
|
^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:16: note: in
expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK'
173 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:2: note: in
expansion of macro 'LE_SF'
184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:2: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20'
404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:3: note: in
expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201'
411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:61:
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in
expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[0].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in
expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in
expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[0].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:2: note: in
expansion of macro 'tf_regs'
469 | tf_regs(0),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in
expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[1].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in
expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in
expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[1].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:2: note: in
expansion of macro 'tf_regs'
470 | tf_regs(1),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in
expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[2].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in
expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in
expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[2].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:2: note: in
expansion of macro 'tf_regs'
471 | tf_regs(2),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in
expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[3].CURSOR_CONTROL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:2: note: in expansion of
macro 'SRI'
181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in
expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
>
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: error:
initialized field overwritten [-Werror=override-init]
247 | #define
DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in
expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near
initialization for 'tf_regs[3].DSCL_MEM_PWR_CTRL')
247 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in
expansion of macro 'DMU_BASE__INST0_SEG2'
247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in
expansion of macro 'BASE_INNER'
249 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:14: note: in
expansion of macro 'BASE'
256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:2: note: in expansion of
macro 'SRI'
183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:2: note: in expansion
of macro 'TF_REG_LIST_DCN20'
34 | TF_REG_LIST_DCN20(id)
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:2: note: in
expansion of macro 'TF_REG_LIST_DCN201'
465 | TF_REG_LIST_DCN201(id),\
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:2: note: in
expansion of macro 'tf_regs'
472 | tf_regs(3),
| ^~~~~~~
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: error:
initialized field overwritten [-Werror=override-init]
5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT
0x0
|
^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of
macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:2: note: in expansion of
macro 'TF_SF'
368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:2: note: in expansion of
macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON'
547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion
of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in
expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: note:
(near initialization for 'tf_shift.CM_3DLUT_MODE')
5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT
0x0
|
^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of
macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:2: note: in expansion of
macro 'TF_SF'
368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:2: note: in expansion of
macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON'
547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion
of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in
expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5183:111: error:
initialized field overwritten [-Werror=override-init]
5183 | #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT
0x0
|
^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of
macro 'CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:206:2: note: in expansion of
macro 'TF_SF'
206 | TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:548:2: note: in expansion of
macro 'TF_REG_LIST_SH_MASK_DCN20_UPDATED'
548 | TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:2: note: in expansion
of macro 'TF_REG_LIST_SH_MASK_DCN20'
37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:3: note: in
expansion of macro 'TF_REG_LIST_SH_MASK_DCN201'
..
vim +/to_dal_irq_source_dcn201 +42
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c
41
42 enum dc_irq_source to_dal_irq_source_dcn201(
43 struct
irq_service *irq_service,
44 uint32_t src_id,
45 uint32_t ext_id)
46 {
47 switch (src_id) {
48 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK1;
50 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK2;
52 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
53 return DC_IRQ_SOURCE_DC1_VLINE0;
54 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
55 return DC_IRQ_SOURCE_DC2_VLINE0;
56 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
57 return DC_IRQ_SOURCE_PFLIP1;
58 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
59 return DC_IRQ_SOURCE_PFLIP2;
60 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
61 return DC_IRQ_SOURCE_VUPDATE1;
62 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
63 return DC_IRQ_SOURCE_VUPDATE2;
64 case DCN_1_0__SRCID__DC_HPD1_INT:
65 /* generic src_id for all HPD and HPDRX interrupts */
66 switch (ext_id) {
67 case DCN_1_0__CTXID__DC_HPD1_INT:
68 return DC_IRQ_SOURCE_HPD1;
69 case DCN_1_0__CTXID__DC_HPD2_INT:
70 return DC_IRQ_SOURCE_HPD2;
71 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
72 return DC_IRQ_SOURCE_HPD1RX;
73 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
74 return DC_IRQ_SOURCE_HPD2RX;
75 default:
76 return DC_IRQ_SOURCE_INVALID;
77 }
78 break;
79
80 default:
81 return DC_IRQ_SOURCE_INVALID;
82 }
83 return DC_IRQ_SOURCE_INVALID;
84 }
85
86 static bool hpd_ack(
87 struct irq_service *irq_service,
88 const struct irq_source_info *info)
89 {
90 uint32_t addr = info->status_reg;
91 uint32_t value = dm_read_reg(irq_service->ctx, addr);
92 uint32_t current_status =
93 get_reg_field_value(
94 value,
95 HPD0_DC_HPD_INT_STATUS,
96 DC_HPD_SENSE_DELAYED);
97
98 dal_irq_service_ack_generic(irq_service, info);
99
100 value = dm_read_reg(irq_service->ctx, info->enable_reg);
101
102 set_reg_field_value(
103 value,
104 current_status ? 0 : 1,
105 HPD0_DC_HPD_INT_CONTROL,
106 DC_HPD_INT_POLARITY);
107
108 dm_write_reg(irq_service->ctx, info->enable_reg, value);
109
110 return true;
111 }
112
113 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
114 .set = NULL,
115 .ack = hpd_ack
116 };
117
118 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
119 .set = NULL,
120 .ack = NULL
121 };
122
123 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
124 .set = NULL,
125 .ack = NULL
126 };
127
128 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
129 .set = NULL,
130 .ack = NULL
131 };
132
133 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
134 .set = NULL,
135 .ack = NULL
136 };
137 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
138 .set = NULL,
139 .ack = NULL
140 };
141
142 static const struct irq_source_info_funcs
dmub_outbox_irq_info_funcs = {
143 .set = NULL,
144 .ack = NULL
145 };
146
---
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