tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto head: 10c3d69bc60059b194dcfa816cbc1240ffb0431d commit: 94e13c2880167751eb5cbbcb0e7be68ca83f0653 [9356/18530] dmaengine: dw-axi-dma: support cyclic mode config: ia64-randconfig-s031-20210930 (attached as .config) compiler: ia64-linux-gcc (GCC) 11.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.4-dirty # https://github.com/intel/linux-intel-lts/commit/94e13c2880167751eb5cbbcb0... git remote add intel-lts https://github.com/intel/linux-intel-lts.git git fetch --no-tags intel-lts 5.4/yocto git checkout 94e13c2880167751eb5cbbcb0e7be68ca83f0653 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; sparse warnings: (new ones prefixed by >>) drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: expected restricted __le32 [usertype] block_ts_lo drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:993:47: sparse: got unsigned long drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: expected restricted __le32 [usertype] block_ts_lo drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1068:55: sparse: got unsigned long drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] block_ts_lo @@ got unsigned long @@ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: expected restricted __le32 [usertype] block_ts_lo drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1070:55: sparse: got unsigned long drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected unsigned int [usertype] irq_mask @@ got restricted __le32 [usertype] status_lo @@ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: expected unsigned int [usertype] irq_mask drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1169:59: sparse: got restricted __le32 [usertype] status_lo drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: sparse: invalid assignment: |= drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: left side has type restricted __le32 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1170:42: sparse: right side has type unsigned long drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:1111:22: sparse: sparse: context imbalance in 'axi_chan_handle_err' - different lock contexts for basic block vim +993 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c 912 913 static struct dma_async_tx_descriptor * 914 dw_chan_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr, 915 size_t buf_len, size_t period_len, 916 enum dma_transfer_direction direction, 917 unsigned long flags) 918 { 919 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 920 struct axi_dma_desc *first = NULL, *prev = NULL; 921 unsigned int reg_width; 922 unsigned int mem_width; 923 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); 924 dma_addr_t reg; 925 u32 reg_value = 0; 926 unsigned int i = 0; 927 u32 ctllo, ctlhi; 928 size_t total_len = 0; 929 size_t block_ts, max_block_ts; 930 u8 lms = 0; // Select AXI0 master for LLI fetching 931 u32 offset; 932 933 if (unlikely(!is_slave_direction(direction))) 934 return NULL; 935 936 chan->direction = direction; 937 chan->cyclic = 0x1; 938 939 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 940 941 axi_set_hw_channel(chan->chip, chan->hw_hs_num); 942 943 switch (direction) { 944 case DMA_MEM_TO_DEV: 945 reg_width = __ffs(chan->slave_config.dst_addr_width); 946 947 chan->reg_width = reg_width; 948 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) { 949 offset = DMAC_APB_HALFWORD_WR_CH_EN; 950 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 951 reg_value |= 0x1 << chan->id; 952 axi_dma_apb_iowrite32(chan->chip, 953 DMAC_APB_HALFWORD_WR_CH_EN, reg_value); 954 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) { 955 offset = DMAC_APB_BYTE_WR_CH_EN; 956 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 957 reg_value |= 0x1 << chan->id; 958 axi_dma_apb_iowrite32(chan->chip, offset, reg_value); 959 } 960 reg = chan->slave_config.dst_addr; 961 962 ctllo = axi_dma_prepare_ctllo(chan) | 963 reg_width << CH_CTL_L_DST_WIDTH_POS | 964 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | 965 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; 966 967 for (i = 0; i < buf_len / period_len; i++) { 968 struct axi_dma_desc *desc; 969 size_t xfer_len; 970 u32 mem, len; 971 972 mem_width = __ffs(data_width | mem | len); 973 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 974 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 975 976 xfer_len = period_len; 977 block_ts = period_len; 978 979 desc = axi_desc_get(chan); 980 if (unlikely(!desc)) 981 goto err_desc_get; 982 983 if (block_ts > max_block_ts) { 984 block_ts = max_block_ts; 985 xfer_len = max_block_ts << mem_width; 986 } 987 988 ctlhi = axi_dma_prepare_ctlhi(chan); 989 990 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS; 991 write_desc_sar(desc, buf_addr + i * period_len); 992 write_desc_dar(desc, reg); 994 desc->lli.ctl_hi = cpu_to_le32(ctlhi); 995 desc->lli.ctl_lo = cpu_to_le32(ctllo); 996 997 set_desc_src_master(desc); 998 set_desc_src_master(desc); 999 1000 // Manage transfer list (xfer_list) 1001 if (!first) { 1002 first = desc; 1003 } else { 1004 write_desc_llp(prev, desc->vd.tx.phys | lms); 1005 list_add_tail(&desc->xfer_list, 1006 &first->xfer_list); 1007 } 1008 prev = desc; 1009 if (i == ((buf_len / period_len) - 1)) 1010 write_desc_llp(prev, first->vd.tx.phys | lms); 1011 1012 total_len += xfer_len; 1013 1014 set_desc_last(desc); 1015 } 1016 break; 1017 case DMA_DEV_TO_MEM: 1018 reg_width = __ffs(chan->slave_config.src_addr_width); 1019 1020 chan->reg_width = reg_width; 1021 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) { 1022 offset = DMAC_APB_HALFWORD_WR_CH_EN; 1023 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 1024 reg_value |= 0x1 << chan->id; 1025 axi_dma_apb_iowrite32(chan->chip, offset, reg_value); 1026 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) { 1027 offset = DMAC_APB_BYTE_WR_CH_EN; 1028 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 1029 reg_value |= 0x1 << chan->id; 1030 axi_dma_apb_iowrite32(chan->chip, offset, reg_value); 1031 } 1032 reg = chan->slave_config.src_addr; 1033 if (reg_width > DWAXIDMAC_TRANS_WIDTH_32) 1034 reg_width = DWAXIDMAC_TRANS_WIDTH_32; 1035 ctllo = axi_dma_prepare_ctllo(chan) | 1036 reg_width << CH_CTL_L_SRC_WIDTH_POS | 1037 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 1038 // Workaround 1039 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; 1040 1041 for (i = 0; i < buf_len / period_len; i++) { 1042 struct axi_dma_desc *desc; 1043 size_t xfer_len; 1044 u32 mem, len; 1045 1046 desc = axi_desc_get(chan); 1047 if (unlikely(!desc)) 1048 goto err_desc_get; 1049 1050 xfer_len = len; 1051 block_ts = xfer_len >> reg_width; 1052 if (block_ts > max_block_ts) { 1053 block_ts = max_block_ts; 1054 xfer_len = max_block_ts << reg_width; 1055 } 1056 xfer_len = period_len; 1057 block_ts = period_len; 1058 mem_width = __ffs(data_width | mem | xfer_len); 1059 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 1060 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 1061 1062 ctlhi = axi_dma_prepare_ctlhi(chan); 1063 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS; 1064 1065 write_desc_sar(desc, reg); 1066 write_desc_dar(desc, buf_addr + i * period_len); 1067 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) 1068 desc->lli.block_ts_lo = period_len / 2; 1069 else if (reg_width >= DWAXIDMAC_TRANS_WIDTH_32) 1070 desc->lli.block_ts_lo = period_len / 4; 1071 desc->lli.ctl_hi = cpu_to_le32(ctlhi); 1072 desc->lli.ctl_lo = cpu_to_le32(ctllo); 1073 1074 set_desc_src_master(desc); 1075 set_desc_src_master(desc); 1076 1077 // Manage transfer list (xfer_list) 1078 if (!first) { 1079 first = desc; 1080 } else { 1081 write_desc_llp(prev, desc->vd.tx.phys | lms); 1082 list_add_tail(&desc->xfer_list, 1083 &first->xfer_list); 1084 } 1085 prev = desc; 1086 if (i == ((buf_len / period_len) - 1)) 1087 write_desc_llp(prev, first->vd.tx.phys | lms); 1088 1089 total_len += xfer_len; 1090 1091 // TODO: check if needed 1092 set_desc_last(desc); 1093 } 1094 break; 1095 default: 1096 return NULL; 1097 } 1098 1099 if (unlikely(!first)) 1100 return NULL; 1101 1102 return vchan_tx_prep(&chan->vc, &first->vd, flags); 1103 1104 err_desc_get: 1105 if (first) 1106 axi_desc_put(first); 1107 1108 return NULL; 1109 } 1110 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org