tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/urgent head: 76e2fc63ca40977af893b724b00cc2f8e9ce47a4 commit: 76e2fc63ca40977af893b724b00cc2f8e9ce47a4 [2/2] x86/cpu/amd: Set __max_die_per_package on AMD config: i386-randconfig-r015-20210113 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=76... git remote add tip https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git git fetch --no-tags tip x86/urgent git checkout 76e2fc63ca40977af893b724b00cc2f8e9ce47a4 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): arch/x86/kernel/cpu/amd.c: In function 'bsp_init_amd': 545 | __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1; | ^~~~~~~~~~~~~~~~~~~~~ | topology_max_die_per_package arch/x86/kernel/cpu/amd.c:545:3: note: each undeclared identifier is reported only once for each function it appears in vim +545 arch/x86/kernel/cpu/amd.c 508 509 static void bsp_init_amd(struct cpuinfo_x86 *c) 510 { 511 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 512 513 if (c->x86 > 0x10 || 514 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 515 u64 val; 516 517 rdmsrl(MSR_K7_HWCR, val); 518 if (!(val & BIT(24))) 519 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 520 } 521 } 522 523 if (c->x86 == 0x15) { 524 unsigned long upperbit; 525 u32 cpuid, assoc; 526 527 cpuid = cpuid_edx(0x80000005); 528 assoc = cpuid >> 16 & 0xff; 529 upperbit = ((cpuid >> 24) << 10) / assoc; 530 531 va_align.mask = (upperbit - 1) & PAGE_MASK; 532 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 533 534 /* A random value per boot for bit slice [12:upper_bit) */ 535 va_align.bits = get_random_int() & va_align.mask; 536 } 537 538 if (cpu_has(c, X86_FEATURE_MWAITX)) 539 use_mwaitx_delay(); 540 541 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 542 u32 ecx; 543 544 ecx = cpuid_ecx(0x8000001e); 546 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 547 u64 value; 548 549 rdmsrl(MSR_FAM10H_NODE_ID, value); 550 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1; 551 } 552 553 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 554 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 555 c->x86 >= 0x15 && c->x86 <= 0x17) { 556 unsigned int bit; 557 558 switch (c->x86) { 559 case 0x15: bit = 54; break; 560 case 0x16: bit = 33; break; 561 case 0x17: bit = 10; break; 562 default: return; 563 } 564 /* 565 * Try to cache the base value so further operations can 566 * avoid RMW. If that faults, do not enable SSBD. 567 */ 568 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 569 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 570 setup_force_cpu_cap(X86_FEATURE_SSBD); 571 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 572 } 573 } 574 575 resctrl_cpu_detect(c); 576 } 577 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org