Hi Dmitry,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on v5.16-rc5 next-20211214]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/clk-qcom-anothe...
base:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: riscv-randconfig-r011-20211214
(
https://download.01.org/0day-ci/archive/20211215/202112151937.olimzu4n-lk...)
compiler: clang version 14.0.0 (
https://github.com/llvm/llvm-project
dd245bab9fbb364faa1581e4f92ba3119a872fba)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
#
https://github.com/0day-ci/linux/commit/a93be2f54e6825699913bbe0aab77dd7e...
git remote add linux-review
https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Dmitry-Baryshkov/clk-qcom-another-round-of-clock-drivers-cleanup/20211215-085637
git checkout a93be2f54e6825699913bbe0aab77dd7e4837fde
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir
ARCH=riscv SHELL=/bin/bash drivers/clk/qcom/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
> drivers/clk/qcom/gpucc-sdm660.c:208:24: error: no member named
'clr' in 'struct clk_rcg2'; did you mean 'clkr'?
&rbbmtimer_clk_src.clr.hw,
^~~
clkr
drivers/clk/qcom/clk-rcg.h:150:20: note: 'clkr' declared here
struct clk_regmap clkr;
^
1 error generated.
vim +208 drivers/clk/qcom/gpucc-sdm660.c
198
199 static struct clk_branch gpucc_rbbmtimer_clk = {
200 .halt_reg = 0x10d0,
201 .halt_check = BRANCH_HALT,
202 .clkr = {
203 .enable_reg = 0x10d0,
204 .enable_mask = BIT(0),
205 .hw.init = &(struct clk_init_data){
206 .name = "gpucc_rbbmtimer_clk",
207 .parent_hws = (const struct clk_hw*[]){
208 &rbbmtimer_clk_src.clr.hw,
209 },
210 .num_parents = 1,
211 .flags = CLK_SET_RATE_PARENT,
212 .ops = &clk_branch2_ops,
213 },
214 },
215 };
216
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org