tree: https://github.com/intel/linux-intel-lts.git 5.4/preempt-rt head: 646a89c49751509d6493602ca6df16e229574d24 commit: 2e228f3df9479e9e061cc7e0b7aba0c071ea22bf [14488/19036] REVERT-ME: Temporary Enable D0i3 flow for PSE IOs config: x86_64-randconfig-a001-20211021 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 3cea2505fd8d99a9ba0cb625aecfe28a47c4e3f8) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel/linux-intel-lts/commit/2e228f3df9479e9e061cc7e0b... git remote add intel-lts https://github.com/intel/linux-intel-lts.git git fetch --no-tags intel-lts 5.4/preempt-rt git checkout 2e228f3df9479e9e061cc7e0b7aba0c071ea22bf # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): u32 cgsr_reg; ^ 1 warning generated. vim +/cgsr_reg +333 drivers/pwm/pwm-dwc.c 325 326 #ifdef CONFIG_PM 327 static int dwc_pci_runtime_suspend(struct device *dev) 328 { 329 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 330 struct dwc_pwm *dwc = pci_get_drvdata(pdev); 331 unsigned long j0, j1, delay; 332 u32 d0i3c_reg; 334 335 delay = msecs_to_jiffies(100); 336 j0 = jiffies; 337 j1 = j0 + delay; 338 339 cgsr_reg = dwc_readl(dwc->base, DWC_TIM_CGSR); 340 dwc_writel(dwc->base, DWC_TIM_CGSR_CG, DWC_TIM_CGSR); 341 342 d0i3c_reg = dwc_readl(dwc->base, DWC_TIM_D0I3C); 343 344 if (d0i3c_reg & DWC_TIM_D0I3_CIP) { 345 dev_info(dev, "%s d0i3c CIP detected", __func__); 346 } else { 347 dwc_writel(dwc->base, DWC_TIM_D0I3_EN, DWC_TIM_D0I3C); 348 d0i3c_reg = dwc_readl(dwc->base, DWC_TIM_D0I3C); 349 } 350 351 while (time_before(jiffies, j1)) { 352 d0i3c_reg = dwc_readl(dwc->base, DWC_TIM_D0I3C); 353 if (!(d0i3c_reg & DWC_TIM_D0I3_CIP)) 354 break; 355 } 356 357 if (d0i3c_reg & DWC_TIM_D0I3_CIP) 358 dev_info(dev, "%s: timeout waiting CIP to be cleared", 359 __func__); 360 /* 361 * The PCI core will handle transition to D3 automatically. We only 362 * need to provide runtime PM hooks for that to happen. 363 */ 364 365 return 0; 366 } 367 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org