Hi Rob, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on v5.8-rc2] [also build test WARNING on next-20200708] [cannot apply to tip/perf/core arm64/for-next/core arm-perf/for-next/perf linus/master v5.8-rc4 v5.8-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Rob-Herring/arm64-Enable-access-... base: 48778464bb7d346b47157d21ffde2af6b2d39110 config: arm64-allyesconfig (attached as .config) compiler: aarch64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): arch/arm64/kernel/perf_event.c:139:41: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD' 139 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:84:45: warning: initialized field overwritten [-Woverride-init] 84 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41 | ^~~~ arch/arm64/kernel/perf_event.c:140:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR' 140 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:84:45: note: (near initialization for 'armv8_vulcan_perf_cache_map[0][1][0]') 84 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41 | ^~~~ arch/arm64/kernel/perf_event.c:140:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR' 140 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:86:51: warning: initialized field overwritten [-Woverride-init] 86 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43 | ^~~~ arch/arm64/kernel/perf_event.c:141:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR' 141 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:86:51: note: (near initialization for 'armv8_vulcan_perf_cache_map[0][1][1]') 86 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43 | ^~~~ arch/arm64/kernel/perf_event.c:141:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR' 141 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:95:44: warning: initialized field overwritten [-Woverride-init] 95 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E | ^~~~ arch/arm64/kernel/perf_event.c:143:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD' 143 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:95:44: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][0][0]') 95 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E | ^~~~ arch/arm64/kernel/perf_event.c:143:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD' 143 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:96:44: warning: initialized field overwritten [-Woverride-init] 96 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F | ^~~~ arch/arm64/kernel/perf_event.c:144:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR' 144 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:96:44: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][1][0]') 96 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F | ^~~~ arch/arm64/kernel/perf_event.c:144:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR' 144 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:93:50: warning: initialized field overwritten [-Woverride-init] 93 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C | ^~~~ arch/arm64/kernel/perf_event.c:145:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD' 145 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:93:50: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][0][1]') 93 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C | ^~~~ arch/arm64/kernel/perf_event.c:145:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD' 145 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:94:50: warning: initialized field overwritten [-Woverride-init] 94 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D | ^~~~ arch/arm64/kernel/perf_event.c:146:43: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR' 146 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:94:50: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][1][1]') 94 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D | ^~~~ arch/arm64/kernel/perf_event.c:146:43: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR' 146 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:110:46: warning: initialized field overwritten [-Woverride-init] 110 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60 | ^~~~ arch/arm64/kernel/perf_event.c:148:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD' 148 | [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:110:46: note: (near initialization for 'armv8_vulcan_perf_cache_map[6][0][0]') 110 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60 | ^~~~ arch/arm64/kernel/perf_event.c:148:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD' 148 | [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:111:46: warning: initialized field overwritten [-Woverride-init] 111 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61 | ^~~~ arch/arm64/kernel/perf_event.c:149:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR' 149 | [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/include/asm/perf_event.h:111:46: note: (near initialization for 'armv8_vulcan_perf_cache_map[6][1][0]') 111 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61 | ^~~~ arch/arm64/kernel/perf_event.c:149:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR' 149 | [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/arm64/kernel/perf_event.c: In function 'emulate_pmu': 998 | u32 sys_reg, rt; | ^~~~~~~ vim +/sys_reg +998 arch/arm64/kernel/perf_event.c 995 996 static int emulate_pmu(struct pt_regs *regs, u32 insn) 997 { 999 u32 pmuserenr; 1000 1001 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 1002 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 1003 pmuserenr = read_sysreg(pmuserenr_el0); 1004 1005 if ((pmuserenr & (ARMV8_PMU_USERENR_ER|ARMV8_PMU_USERENR_CR)) != 1006 (ARMV8_PMU_USERENR_ER|ARMV8_PMU_USERENR_CR)) 1007 return -EINVAL; 1008 1009 1010 /* 1011 * Userspace is expected to only use this in the context of the scheme 1012 * described in the struct perf_event_mmap_page comments. 1013 * 1014 * Given that context, we can only get here if we got migrated between 1015 * getting the register index and doing the MSR read. This in turn 1016 * implies we'll fail the sequence and retry, so any value returned is 1017 * 'good', all we need is to be non-fatal. 1018 * 1019 * The choice of the value 0 is comming from the fact that when 1020 * accessing a register which is not counting events but is accessible, 1021 * we get 0. 1022 */ 1023 pt_regs_write_reg(regs, rt, 0); 1024 1025 arm64_skip_faulting_instruction(regs, 4); 1026 return 0; 1027 } 1028 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org