tree: https://github.com/Xilinx/linux-xlnx master head: ebc67ce2d1e7fa15806c226e2461ffd7b42cd188 commit: bff352467d6de71ba0aa62e0cd6c9e98f7e4f293 [9801/10253] net: xilinx: Add support for PL TSN IP features config: i386-randconfig-m021-20200920 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; New smatch warnings: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1608 axienet_open() warn: inconsistent indenting drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1832 axienet_stop() warn: inconsistent indenting Old smatch warnings: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:214 axienet_dma_bd_init() error: uninitialized symbol 'ret'. drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1610 axienet_open() warn: inconsistent indenting drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1839 axienet_stop() warn: inconsistent indenting # https://github.com/Xilinx/linux-xlnx/commit/bff352467d6de71ba0aa62e0cd6c9... git remote add xlnx https://github.com/Xilinx/linux-xlnx git fetch --no-tags xlnx master git checkout bff352467d6de71ba0aa62e0cd6c9e98f7e4f293 vim +1608 drivers/net/ethernet/xilinx/xilinx_axienet_main.c 71c6c837a0fe9d2 Xiaotian Feng 2012-11-13 1601 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1602 /* Enable NAPI scheduling before enabling Axi DMA Rx IRQ, or you 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1603 * might run into a race condition; the RX ISR disables IRQ processing 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1604 * before scheduling the NAPI function to complete the processing. 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1605 * If NAPI scheduling is (still) disabled at that time, no more RX IRQs 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1606 * will be processed as only the NAPI function re-enables them! 57b6ef54c85dd8c Appana Durga Kedareswara Rao 2020-01-24 1607 */ 0f447249ba48721 Saurabh Sengar 2020-01-24 @1608 napi_enable(&lp->napi[i]); 0f447249ba48721 Saurabh Sengar 2020-01-24 1609 } 0f447249ba48721 Saurabh Sengar 2020-01-24 1610 for_each_tx_dma_queue(lp, i) { 0f447249ba48721 Saurabh Sengar 2020-01-24 1611 struct axienet_dma_q *q = lp->dq[i]; 0f447249ba48721 Saurabh Sengar 2020-01-24 1612 #ifdef CONFIG_AXIENET_HAS_MCDMA 0f447249ba48721 Saurabh Sengar 2020-01-24 1613 /* Enable interrupts for Axi MCDMA Tx */ 0f447249ba48721 Saurabh Sengar 2020-01-24 1614 ret = request_irq(q->tx_irq, axienet_mcdma_tx_irq, 0f447249ba48721 Saurabh Sengar 2020-01-24 1615 IRQF_SHARED, ndev->name, ndev); 0f447249ba48721 Saurabh Sengar 2020-01-24 1616 if (ret) 0f447249ba48721 Saurabh Sengar 2020-01-24 1617 goto err_tx_irq; 0f447249ba48721 Saurabh Sengar 2020-01-24 1618 #else 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1619 /* Enable interrupts for Axi DMA Tx */ 0f447249ba48721 Saurabh Sengar 2020-01-24 1620 ret = request_irq(q->tx_irq, axienet_tx_irq, 0f447249ba48721 Saurabh Sengar 2020-01-24 1621 0, ndev->name, ndev); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1622 if (ret) 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1623 goto err_tx_irq; 0f447249ba48721 Saurabh Sengar 2020-01-24 1624 #endif 0f447249ba48721 Saurabh Sengar 2020-01-24 1625 } 0f447249ba48721 Saurabh Sengar 2020-01-24 1626 0f447249ba48721 Saurabh Sengar 2020-01-24 1627 for_each_rx_dma_queue(lp, i) { 0f447249ba48721 Saurabh Sengar 2020-01-24 1628 struct axienet_dma_q *q = lp->dq[i]; 0f447249ba48721 Saurabh Sengar 2020-01-24 1629 #ifdef CONFIG_AXIENET_HAS_MCDMA 0f447249ba48721 Saurabh Sengar 2020-01-24 1630 /* Enable interrupts for Axi MCDMA Rx */ 0f447249ba48721 Saurabh Sengar 2020-01-24 1631 ret = request_irq(q->rx_irq, axienet_mcdma_rx_irq, 0f447249ba48721 Saurabh Sengar 2020-01-24 1632 IRQF_SHARED, ndev->name, ndev); 0f447249ba48721 Saurabh Sengar 2020-01-24 1633 if (ret) 0f447249ba48721 Saurabh Sengar 2020-01-24 1634 goto err_rx_irq; 0f447249ba48721 Saurabh Sengar 2020-01-24 1635 #else 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1636 /* Enable interrupts for Axi DMA Rx */ 0f447249ba48721 Saurabh Sengar 2020-01-24 1637 ret = request_irq(q->rx_irq, axienet_rx_irq, 0f447249ba48721 Saurabh Sengar 2020-01-24 1638 0, ndev->name, ndev); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1639 if (ret) 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1640 goto err_rx_irq; 0f447249ba48721 Saurabh Sengar 2020-01-24 1641 #endif 0f447249ba48721 Saurabh Sengar 2020-01-24 1642 } bff352467d6de71 Saurabh Sengar 2020-02-13 1643 } bff352467d6de71 Saurabh Sengar 2020-02-13 1644 #ifdef CONFIG_XILINX_TSN_PTP bff352467d6de71 Saurabh Sengar 2020-02-13 1645 if (lp->is_tsn) { bff352467d6de71 Saurabh Sengar 2020-02-13 1646 INIT_WORK(&lp->tx_tstamp_work, axienet_tx_tstamp); bff352467d6de71 Saurabh Sengar 2020-02-13 1647 skb_queue_head_init(&lp->ptp_txq); bff352467d6de71 Saurabh Sengar 2020-02-13 1648 bff352467d6de71 Saurabh Sengar 2020-02-13 1649 lp->ptp_rx_hw_pointer = 0; bff352467d6de71 Saurabh Sengar 2020-02-13 1650 lp->ptp_rx_sw_pointer = 0xff; bff352467d6de71 Saurabh Sengar 2020-02-13 1651 bff352467d6de71 Saurabh Sengar 2020-02-13 1652 axienet_iow(lp, PTP_RX_CONTROL_OFFSET, PTP_RX_PACKET_CLEAR); bff352467d6de71 Saurabh Sengar 2020-02-13 1653 bff352467d6de71 Saurabh Sengar 2020-02-13 1654 ret = request_irq(lp->ptp_rx_irq, axienet_ptp_rx_irq, bff352467d6de71 Saurabh Sengar 2020-02-13 1655 0, "ptp_rx", ndev); bff352467d6de71 Saurabh Sengar 2020-02-13 1656 if (ret) bff352467d6de71 Saurabh Sengar 2020-02-13 1657 goto err_ptp_rx_irq; bff352467d6de71 Saurabh Sengar 2020-02-13 1658 bff352467d6de71 Saurabh Sengar 2020-02-13 1659 ret = request_irq(lp->ptp_tx_irq, axienet_ptp_tx_irq, bff352467d6de71 Saurabh Sengar 2020-02-13 1660 0, "ptp_tx", ndev); bff352467d6de71 Saurabh Sengar 2020-02-13 1661 if (ret) bff352467d6de71 Saurabh Sengar 2020-02-13 1662 goto err_ptp_rx_irq; bff352467d6de71 Saurabh Sengar 2020-02-13 1663 } bff352467d6de71 Saurabh Sengar 2020-02-13 1664 #endif 0f447249ba48721 Saurabh Sengar 2020-01-24 1665 d840cf16b08d406 Radhey Shyam Pandey 2020-01-29 1666 if (lp->phy_mode == XXE_PHY_TYPE_USXGMII) { 7546597bc63f5c2 Harini Katakam 2020-01-24 1667 netdev_dbg(ndev, "RX reg: 0x%x\n", 7546597bc63f5c2 Harini Katakam 2020-01-24 1668 axienet_ior(lp, XXV_RCW1_OFFSET)); 7546597bc63f5c2 Harini Katakam 2020-01-24 1669 /* USXGMII setup at selected speed */ 7546597bc63f5c2 Harini Katakam 2020-01-24 1670 reg = axienet_ior(lp, XXV_USXGMII_AN_OFFSET); 7546597bc63f5c2 Harini Katakam 2020-01-24 1671 reg &= ~USXGMII_RATE_MASK; 7546597bc63f5c2 Harini Katakam 2020-01-24 1672 netdev_dbg(ndev, "usxgmii_rate %d\n", lp->usxgmii_rate); 7546597bc63f5c2 Harini Katakam 2020-01-24 1673 switch (lp->usxgmii_rate) { 7546597bc63f5c2 Harini Katakam 2020-01-24 1674 case SPEED_1000: 7546597bc63f5c2 Harini Katakam 2020-01-24 1675 reg |= USXGMII_RATE_1G; 7546597bc63f5c2 Harini Katakam 2020-01-24 1676 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1677 case SPEED_2500: 7546597bc63f5c2 Harini Katakam 2020-01-24 1678 reg |= USXGMII_RATE_2G5; 7546597bc63f5c2 Harini Katakam 2020-01-24 1679 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1680 case SPEED_10: 7546597bc63f5c2 Harini Katakam 2020-01-24 1681 reg |= USXGMII_RATE_10M; 7546597bc63f5c2 Harini Katakam 2020-01-24 1682 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1683 case SPEED_100: 7546597bc63f5c2 Harini Katakam 2020-01-24 1684 reg |= USXGMII_RATE_100M; 7546597bc63f5c2 Harini Katakam 2020-01-24 1685 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1686 case SPEED_5000: 7546597bc63f5c2 Harini Katakam 2020-01-24 1687 reg |= USXGMII_RATE_5G; 7546597bc63f5c2 Harini Katakam 2020-01-24 1688 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1689 case SPEED_10000: 7546597bc63f5c2 Harini Katakam 2020-01-24 1690 reg |= USXGMII_RATE_10G; 7546597bc63f5c2 Harini Katakam 2020-01-24 1691 break; 7546597bc63f5c2 Harini Katakam 2020-01-24 1692 default: 7546597bc63f5c2 Harini Katakam 2020-01-24 1693 reg |= USXGMII_RATE_1G; 7546597bc63f5c2 Harini Katakam 2020-01-24 1694 } 7546597bc63f5c2 Harini Katakam 2020-01-24 1695 reg |= USXGMII_FD; 7546597bc63f5c2 Harini Katakam 2020-01-24 1696 reg |= (USXGMII_EN | USXGMII_LINK_STS); 7546597bc63f5c2 Harini Katakam 2020-01-24 1697 axienet_iow(lp, XXV_USXGMII_AN_OFFSET, reg); 7546597bc63f5c2 Harini Katakam 2020-01-24 1698 reg |= USXGMII_AN_EN; 7546597bc63f5c2 Harini Katakam 2020-01-24 1699 axienet_iow(lp, XXV_USXGMII_AN_OFFSET, reg); 7546597bc63f5c2 Harini Katakam 2020-01-24 1700 /* AN Restart bit should be reset, set and then reset as per 7546597bc63f5c2 Harini Katakam 2020-01-24 1701 * spec with a 1 ms delay for a raising edge trigger 7546597bc63f5c2 Harini Katakam 2020-01-24 1702 */ 7546597bc63f5c2 Harini Katakam 2020-01-24 1703 axienet_iow(lp, XXV_USXGMII_AN_OFFSET, 7546597bc63f5c2 Harini Katakam 2020-01-24 1704 reg & ~USXGMII_AN_RESTART); 7546597bc63f5c2 Harini Katakam 2020-01-24 1705 mdelay(1); 7546597bc63f5c2 Harini Katakam 2020-01-24 1706 axienet_iow(lp, XXV_USXGMII_AN_OFFSET, 7546597bc63f5c2 Harini Katakam 2020-01-24 1707 reg | USXGMII_AN_RESTART); 7546597bc63f5c2 Harini Katakam 2020-01-24 1708 mdelay(1); 7546597bc63f5c2 Harini Katakam 2020-01-24 1709 axienet_iow(lp, XXV_USXGMII_AN_OFFSET, 7546597bc63f5c2 Harini Katakam 2020-01-24 1710 reg & ~USXGMII_AN_RESTART); 7546597bc63f5c2 Harini Katakam 2020-01-24 1711 7546597bc63f5c2 Harini Katakam 2020-01-24 1712 /* Check block lock bit to make sure RX path is ok with 7546597bc63f5c2 Harini Katakam 2020-01-24 1713 * USXGMII initialization. 7546597bc63f5c2 Harini Katakam 2020-01-24 1714 */ 7546597bc63f5c2 Harini Katakam 2020-01-24 1715 err = readl_poll_timeout(lp->regs + XXV_STATRX_BLKLCK_OFFSET, 7546597bc63f5c2 Harini Katakam 2020-01-24 1716 reg, (reg & XXV_RX_BLKLCK_MASK), 7546597bc63f5c2 Harini Katakam 2020-01-24 1717 100, DELAY_OF_ONE_MILLISEC); 7546597bc63f5c2 Harini Katakam 2020-01-24 1718 if (err) { 7546597bc63f5c2 Harini Katakam 2020-01-24 1719 netdev_err(ndev, "%s: USXGMII Block lock bit not set", 7546597bc63f5c2 Harini Katakam 2020-01-24 1720 __func__); 7546597bc63f5c2 Harini Katakam 2020-01-24 1721 ret = -ENODEV; 7546597bc63f5c2 Harini Katakam 2020-01-24 1722 goto err_eth_irq; 7546597bc63f5c2 Harini Katakam 2020-01-24 1723 } 7546597bc63f5c2 Harini Katakam 2020-01-24 1724 7546597bc63f5c2 Harini Katakam 2020-01-24 1725 err = readl_poll_timeout(lp->regs + XXV_USXGMII_AN_STS_OFFSET, 7546597bc63f5c2 Harini Katakam 2020-01-24 1726 reg, (reg & USXGMII_AN_STS_COMP_MASK), 7546597bc63f5c2 Harini Katakam 2020-01-24 1727 1000000, DELAY_OF_ONE_MILLISEC); 7546597bc63f5c2 Harini Katakam 2020-01-24 1728 if (err) { 7546597bc63f5c2 Harini Katakam 2020-01-24 1729 netdev_err(ndev, "%s: USXGMII AN not complete", 7546597bc63f5c2 Harini Katakam 2020-01-24 1730 __func__); 7546597bc63f5c2 Harini Katakam 2020-01-24 1731 ret = -ENODEV; 7546597bc63f5c2 Harini Katakam 2020-01-24 1732 goto err_eth_irq; 7546597bc63f5c2 Harini Katakam 2020-01-24 1733 } 7546597bc63f5c2 Harini Katakam 2020-01-24 1734 7546597bc63f5c2 Harini Katakam 2020-01-24 1735 netdev_info(ndev, "USXGMII setup at %d\n", lp->usxgmii_rate); 7546597bc63f5c2 Harini Katakam 2020-01-24 1736 } 7546597bc63f5c2 Harini Katakam 2020-01-24 1737 522856cefaf09d1 Robert Hancock 2019-06-06 1738 /* Enable interrupts for Axi Ethernet core (if defined) */ 9e8ce9d565663fc Appana Durga Kedareswara Rao 2020-01-24 1739 if (!lp->eth_hasnobuf && (lp->axienet_config->mactype == XAXIENET_1G)) { 522856cefaf09d1 Robert Hancock 2019-06-06 1740 ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, 522856cefaf09d1 Robert Hancock 2019-06-06 1741 ndev->name, ndev); 522856cefaf09d1 Robert Hancock 2019-06-06 1742 if (ret) 522856cefaf09d1 Robert Hancock 2019-06-06 1743 goto err_eth_irq; 522856cefaf09d1 Robert Hancock 2019-06-06 1744 } 71c6c837a0fe9d2 Xiaotian Feng 2012-11-13 1745 0f447249ba48721 Saurabh Sengar 2020-01-24 1746 netif_tx_start_all_queues(ndev); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1747 return 0; 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1748 522856cefaf09d1 Robert Hancock 2019-06-06 1749 err_eth_irq: 0f447249ba48721 Saurabh Sengar 2020-01-24 1750 while (i--) { 0f447249ba48721 Saurabh Sengar 2020-01-24 1751 q = lp->dq[i]; 0f447249ba48721 Saurabh Sengar 2020-01-24 1752 free_irq(q->rx_irq, ndev); 0f447249ba48721 Saurabh Sengar 2020-01-24 1753 } 0f447249ba48721 Saurabh Sengar 2020-01-24 1754 i = lp->num_tx_queues; 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1755 err_rx_irq: 0f447249ba48721 Saurabh Sengar 2020-01-24 1756 while (i--) { 0f447249ba48721 Saurabh Sengar 2020-01-24 1757 q = lp->dq[i]; 0f447249ba48721 Saurabh Sengar 2020-01-24 1758 free_irq(q->tx_irq, ndev); 0f447249ba48721 Saurabh Sengar 2020-01-24 1759 } 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1760 err_tx_irq: 0f447249ba48721 Saurabh Sengar 2020-01-24 1761 for_each_rx_dma_queue(lp, i) 0f447249ba48721 Saurabh Sengar 2020-01-24 1762 napi_disable(&lp->napi[i]); d840cf16b08d406 Radhey Shyam Pandey 2020-01-29 1763 if (phydev) d840cf16b08d406 Radhey Shyam Pandey 2020-01-29 1764 phy_disconnect(phydev); d840cf16b08d406 Radhey Shyam Pandey 2020-01-29 1765 phydev = NULL; bff352467d6de71 Saurabh Sengar 2020-02-13 1766 #ifdef CONFIG_XILINX_TSN_PTP bff352467d6de71 Saurabh Sengar 2020-02-13 1767 err_ptp_rx_irq: bff352467d6de71 Saurabh Sengar 2020-02-13 1768 #endif 0f447249ba48721 Saurabh Sengar 2020-01-24 1769 for_each_rx_dma_queue(lp, i) 0f447249ba48721 Saurabh Sengar 2020-01-24 1770 tasklet_kill(&lp->dma_err_tasklet[i]); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1771 dev_err(lp->dev, "request_irq() failed\n"); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1772 return ret; 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1773 } 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 1774 :::::: The code at line 1608 was first introduced by commit :::::: 0f447249ba48721e24292b1ddacf1b4b4e21d9a7 net: axienet: added multichannel DMA support :::::: TO: Saurabh Sengar <saurabh.singh(a)xilinx.com&gt; :::::: CC: Michal Simek <michal.simek(a)xilinx.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org