Hi Sergio, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on clk/clk-next] [also build test WARNING on staging/staging-testing robh/for-next linus/master v5.10-rc3 next-20201113] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Sergio-Paracuellos/MIPS-ralink-a... base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next config: mips-allyesconfig (attached as .config) compiler: mips-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/e9751b3fda8fd54952502ec81fddc61c8... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Sergio-Paracuellos/MIPS-ralink-add-CPU-clock-detection-and-clock-gate-driver-for-MT7621/20201113-171221 git checkout e9751b3fda8fd54952502ec81fddc61c80347155 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/clk/ralink/clk-mt7621.c: In function 'mt7621_register_top_clocks': >> drivers/clk/ralink/clk-mt7621.c:299:3: warning: ignoring return value of 'of_clk_hw_register', declared with attribute warn_unused_result [-Wunused-result] 299 | of_clk_hw_register(clk_prov->node, &sclk->hw); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/ralink/clk-mt7621.c: In function 'mt7621_gate_ops_init': drivers/clk/ralink/clk-mt7621.c:155:2: warning: ignoring return value of 'of_clk_hw_register', declared with attribute warn_unused_result [-Wunused-result] 155 | of_clk_hw_register(np, &sclk->hw); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +/of_clk_hw_register +299 drivers/clk/ralink/clk-mt7621.c 288 289 static void mt7621_register_top_clocks(struct mt7621_clk_provider *clk_prov) 290 { 291 struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data; 292 struct clk_hw **hws = (*clk_data)->hws; 293 int i; 294 295 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { 296 struct mt7621_clk *sclk = &mt7621_clks_base[i]; 297 298 sclk->clk_prov = clk_prov; > 299 of_clk_hw_register(clk_prov->node, &sclk->hw); 300 hws[i] = &sclk->hw; 301 (*clk_data)->num++; 302 } 303 } 304