tree: https://github.com/superna9999/linux amlogic/v5.17/g12-dsi head: 62dac9179f2937dc08bffe08d15c6846bc4aedb4 commit: cc44c3ce92a63f2c59a3f0ac03e6defd41542940 [7/23] WiP: drm/meson: vclk: add DSI clock config config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20211212/202112121520.P5eMl3xJ-lk...) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/superna9999/linux/commit/cc44c3ce92a63f2c59a3f0ac03e6d... git remote add superna9999 https://github.com/superna9999/linux git fetch --no-tags superna9999 amlogic/v5.17/g12-dsi git checkout cc44c3ce92a63f2c59a3f0ac03e6defd41542940 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; Note: the superna9999/amlogic/v5.17/g12-dsi HEAD 62dac9179f2937dc08bffe08d15c6846bc4aedb4 builds fine. It only hurts bisectability. All errors (new ones prefixed by >>): drivers/gpu/drm/meson/meson_vclk.c: In function 'meson_dsi_clock_config': 1035 | meson_vid_pll_set(priv, vid_pll_div); | ^~~~~~~~~~~ drivers/gpu/drm/meson/meson_vclk.c:1035:33: note: each undeclared identifier is reported only once for each function it appears in vim +/vid_pll_div +1035 drivers/gpu/drm/meson/meson_vclk.c 1029 1030 static void meson_dsi_clock_config(struct meson_drm *priv, unsigned freq) 1031 { 1032 meson_hdmi_pll_generic_set(priv, freq); 1033 1034 /* Setup vid_pll divider */ 1036 1037 /* Disable VCLK2 */ 1038 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); 1039 1040 /* Setup vid_pll to /1 */ 1041 meson_vid_pll_set(priv, VID_PLL_DIV_1); 1042 1043 /* Setup the VCLK2 divider value */ 1044 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, 1045 VCLK2_DIV_MASK, 0); 1046 1047 /* select vid_pll for vclk2 */ 1048 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, 1049 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); 1050 1051 /* enable vclk2 gate */ 1052 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); 1053 1054 /* select vclk2_div1 for encl */ 1055 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, 1056 CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT)); 1057 1058 /* release vclk2_div_reset and enable vclk2_div */ 1059 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, 1060 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN); 1061 1062 /* enable vclk2_div1 gate */ 1063 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, 1064 VCLK2_DIV1_EN, VCLK2_DIV1_EN); 1065 1066 /* reset vclk2 */ 1067 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, 1068 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); 1069 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, 1070 VCLK2_SOFT_RESET, 0); 1071 1072 /* enable encl_clk */ 1073 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, 1074 CTS_ENCL_EN, CTS_ENCL_EN); 1075 1076 usleep_range(10000, 11000); 1077 } 1078 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org