tree: https://github.com/esmil/linux visionfive head: fdbe623707a8f3f9b9d2cb3c4c240299a12b8302 commit: c17f07c367229d46348e9005d004d8b3416637bc [59/63] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs config: riscv-randconfig-r015-20220124 (https://download.01.org/0day-ci/archive/20220125/202201250206.q2ugUJBE-lk...) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 7b3d30728816403d1fd73cc5082e9fb761262bce) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/esmil/linux/commit/c17f07c367229d46348e9005d004d8b3416... git remote add esmil https://github.com/esmil/linux git fetch --no-tags esmil visionfive git checkout c17f07c367229d46348e9005d004d8b3416637bc # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/soc/sifive/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/soc/sifive/sifive_l2_cache.c:158:3: error: implicit declaration of function 'writeq' [-Werror,-Wimplicit-function-declaration] writeq(line, l2_base + SIFIVE_L2_FLUSH64); ^ (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + ~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 warning and 1 error generated. vim +148 drivers/soc/sifive/sifive_l2_cache.c a967a289f16969 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 126 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 127 #ifdef CONFIG_SIFIVE_L2_FLUSH c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 128 void sifive_l2_flush64_range(unsigned long start, unsigned long len) c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 129 { c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 130 unsigned long line; c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 131 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 132 if(!l2_base) { c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 133 pr_warn("L2CACHE: base addr invalid, skipping flush\n"); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 134 return; c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 135 } c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 136 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 137 /* TODO: if (len == 0), skipping flush or going on? */ c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 138 if(!len) { c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 139 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 140 return; c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 141 } c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 142 0684fe29f5de5f drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 143 len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN); 0684fe29f5de5f drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 144 start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN); 0684fe29f5de5f drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 145 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 146 /* make sure the address is in the range */ c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 147 if(start < CONFIG_SIFIVE_L2_FLUSH_START || c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @148 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 149 CONFIG_SIFIVE_L2_FLUSH_SIZE)) { b5cf3456431952 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21 150 WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n", c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 151 start, len); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 152 return; c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 153 } c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 154 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 155 mb(); /* sync */ c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 156 for (line = start; line < start + len; c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 157 line += SIFIVE_L2_FLUSH64_LINE_LEN) { c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 158 writeq(line, l2_base + SIFIVE_L2_FLUSH64); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 159 mb(); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 160 } c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 161 } c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range); c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164 :::::: The code at line 148 was first introduced by commit :::::: c6649e71d37210bc4c33eada849aeda98c823de9 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function :::::: TO: Tom <support(a)vamrs.com&gt; :::::: CC: Emil Renner Berthing <kernel(a)esmil.dk&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org