tree: https://github.com/miquelraynal/linux-0day.git perso/nand-next/flags head: c5212e24213cba25bcc57e3bbe0781f3e9d83611 commit: d37a7bc117303ef92516ac07fe2b1e4b4a920e19 [93/102] move keep timings to controller flags config: h8300-randconfig-r004-20200512 (attached as .config) compiler: h8300-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout d37a7bc117303ef92516ac07fe2b1e4b4a920e19 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=h8300 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/mtd/nand/raw/denali.c: In function 'denali_select_target': 216 | if (chip->options & NAND_KEEP_TIMINGS) | ^~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/denali.c:216:22: note: each undeclared identifier is reported only once for each function it appears in vim +/NAND_KEEP_TIMINGS +216 drivers/mtd/nand/raw/denali.c ce082596ae4308 drivers/mtd/nand/denali.c Jason Roberts 2010-05-13 191 f55411427f1c64 drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 192 static void denali_select_target(struct nand_chip *chip, int cs) fa6134e5457d31 drivers/mtd/nand/denali.c Masahiro Yamada 2017-06-13 193 { d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 194 struct denali_controller *denali = to_denali_controller(chip); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 195 struct denali_chip_sel *sel = &to_denali_chip(chip)->sels[cs]; d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 196 struct mtd_info *mtd = nand_to_mtd(chip); fa6134e5457d31 drivers/mtd/nand/denali.c Masahiro Yamada 2017-06-13 197 d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 198 denali->active_bank = sel->bank; d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 199 d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 200 iowrite32(1 << (chip->phys_erase_shift - chip->page_shift), d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 201 denali->reg + PAGES_PER_BLOCK); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 202 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 203 denali->reg + DEVICE_WIDTH); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 204 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 205 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 206 iowrite32(chip->options & NAND_ROW_ADDR_3 ? d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 207 0 : TWO_ROW_ADDR_CYCLES__FLAG, d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 208 denali->reg + TWO_ROW_ADDR_CYCLES); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 209 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 210 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 211 denali->reg + ECC_CORRECTION); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 212 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 213 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 214 iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 215 d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 @216 if (chip->options & NAND_KEEP_TIMINGS) d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 217 return; d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 218 d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 219 /* update timing registers unless NAND_KEEP_TIMINGS is set */ d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 220 iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 221 iowrite32(sel->tcwaw_and_addr_2_data, d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 222 denali->reg + TCWAW_AND_ADDR_2_DATA); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 223 iowrite32(sel->re_2_we, denali->reg + RE_2_WE); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 224 iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 225 iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 226 iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 227 iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); d8e8fd0ebf8b1b drivers/mtd/nand/raw/denali.c Masahiro Yamada 2019-04-02 228 iowrite32(sel->re_2_re, denali->reg + RE_2_RE); fa6134e5457d31 drivers/mtd/nand/denali.c Masahiro Yamada 2017-06-13 229 } fa6134e5457d31 drivers/mtd/nand/denali.c Masahiro Yamada 2017-06-13 230 :::::: The code at line 216 was first introduced by commit :::::: d8e8fd0ebf8b1b8d26a160c2363479a88c1f72c2 mtd: rawnand: denali: decouple controller and NAND chips :::::: TO: Masahiro Yamada <yamada.masahiro(a)socionext.com&gt; :::::: CC: Miquel Raynal <miquel.raynal(a)bootlin.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org