tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 5fcb9628fd1227a5f11d87171cb1b8b5c414d9d9 commit: 0d9283c1695a556c479c4cec9635d0e8aca72d3c [888/2089] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid config: i386-randconfig-s001-20200617 (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.2-rc1-6-g78f577f8-dirty git checkout 0d9283c1695a556c479c4cec9635d0e8aca72d3c # save the attached .config to linux build tree make W=1 C=1 ARCH=i386 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; sparse warnings: (new ones prefixed by >>) drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:128:33: sparse: sparse: cast to restricted __le32 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:128:33: sparse: sparse: cast to restricted __le32 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:128:33: sparse: sparse: cast to restricted __le32 vim +122 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 98 99 /** 100 * vcn_v3_0_sw_init - sw init for VCN block 101 * 102 * @handle: amdgpu_device pointer 103 * 104 * Load firmware and sw initialization 105 */ 106 static int vcn_v3_0_sw_init(void *handle) 107 { 108 struct amdgpu_ring *ring; 109 int i, j, r; 110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 111 112 r = amdgpu_vcn_sw_init(adev); 113 if (r) 114 return r; 115 116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 117 const struct common_firmware_header *hdr; 118 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 121 adev->firmware.fw_size += 123 124 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 125 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 126 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 127 adev->firmware.fw_size += 128 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 129 } 130 DRM_INFO("PSP loading VCN firmware\n"); 131 } 132 133 r = amdgpu_vcn_resume(adev); 134 if (r) 135 return r; 136 137 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 138 if (adev->vcn.harvest_config & (1 << i)) 139 continue; 140 141 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 142 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 143 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 144 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 145 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 146 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 147 148 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 149 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 150 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 151 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 152 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 153 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 154 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 155 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 156 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 157 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 158 159 /* VCN DEC TRAP */ 160 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 161 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 162 if (r) 163 return r; 164 165 ring = &adev->vcn.inst[i].ring_dec; 166 ring->use_doorbell = true; 167 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 168 sprintf(ring->name, "vcn_dec_%d", i); 169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 170 AMDGPU_RING_PRIO_DEFAULT); 171 if (r) 172 return r; 173 174 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 175 /* VCN ENC TRAP */ 176 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 177 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 178 if (r) 179 return r; 180 181 ring = &adev->vcn.inst[i].ring_enc[j]; 182 ring->use_doorbell = true; 183 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 184 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 185 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 186 AMDGPU_RING_PRIO_DEFAULT); 187 if (r) 188 return r; 189 } 190 } 191 192 return 0; 193 } 194 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org