tree: https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git queue-5.4 head: 528c4d782ba8d3c55031b198cd9b9d6c780f067d commit: ff05213f7a694bce80f498aa6f273418cea351a2 [129/131] drm/msm/a6xx: update a6xx_hw_init for A640 and A650 config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout ff05213f7a694bce80f498aa6f273418cea351a2 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/gpu/drm/msm/adreno/a6xx_gpu.c:33:6: warning: no previous prototype for 'a6xx_idle' [-Wmissing-prototypes] 33 | bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) | ^~~~~~~~~ drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a6xx_hw_init': 414 | if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { | ^~~~~~~~~~~~~~ | adreno_is_a540 414 | if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { | ^~~~~~~~~~~~~~ | adreno_is_a540 415 | gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/adreno/a6xx_gpu.c:415:18: note: each undeclared identifier is reported only once for each function it appears in 416 | gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); | ^~~~~~~~~~~~~~~~~~~~~~~ 417 | gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); | ^~~~~~~~~~~~~~~~~~~~~~~ 418 | gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); | ^~~~~~~~~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors # https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git/c... git remote add sashal-linux-stable https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git git fetch --no-tags sashal-linux-stable queue-5.4 git checkout ff05213f7a694bce80f498aa6f273418cea351a2 vim +414 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 362 363 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 364 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 365 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 366 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 367 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 368 A6XX_RBBM_INT_0_MASK_CP_RB | \ 369 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 370 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 371 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 372 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 373 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 374 375 static int a6xx_hw_init(struct msm_gpu *gpu) 376 { 377 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 378 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 379 int ret; 380 381 /* Make sure the GMU keeps the GPU on while we set it up */ 382 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 383 384 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 385 386 /* 387 * Disable the trusted memory range - we don't actually supported secure 388 * memory rendering at this point in time and we don't want to block off 389 * part of the virtual memory space. 390 */ 391 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 392 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 393 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 394 395 /* Turn on 64 bit addressing for all blocks */ 396 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 397 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 398 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 399 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 400 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 401 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 402 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 403 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 404 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 405 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 406 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 407 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 408 409 /* enable hardware clockgating */ 410 a6xx_set_hwcg(gpu, true); 411 412 /* VBIF start */ 413 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 419 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 420 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 421 } else { 422 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 423 } 424 425 /* Make all blocks contribute to the GPU BUSY perf counter */ 426 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 427 428 /* Disable L2 bypass in the UCHE */ 429 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 430 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 431 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 432 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 433 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 434 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 435 436 if (!adreno_is_a650(adreno_gpu)) { 437 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 438 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 439 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 440 441 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 442 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 443 0x00100000 + adreno_gpu->gmem - 1); 444 } 445 446 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 447 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 448 449 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) 450 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 451 else 452 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 453 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 454 455 /* Setting the mem pool size */ 456 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 457 458 /* Setting the primFifo thresholds default values */ 459 if (adreno_is_a650(adreno_gpu)) 460 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); 461 else if (adreno_is_a640(adreno_gpu)) 462 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); 463 else 464 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); 465 466 /* Set the AHB default slave response to "ERROR" */ 467 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 468 469 /* Turn on performance counters */ 470 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 471 472 /* Select CP0 to always count cycles */ 473 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 474 475 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1); 476 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1); 477 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1); 478 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21); 479 480 /* Enable fault detection */ 481 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 482 (1 << 30) | 0x1fffff); 483 484 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 485 486 /* Set weights for bicubic filtering */ 487 if (adreno_is_a650(adreno_gpu)) { 488 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 489 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 490 0x3fe05ff4); 491 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 492 0x3fa0ebee); 493 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 494 0x3f5193ed); 495 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 496 0x3f0243f0); 497 } 498 499 /* Protect registers from the CP */ 500 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 501 502 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 503 A6XX_PROTECT_RDONLY(0x600, 0x51)); 504 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 505 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 506 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 507 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 508 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 509 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 510 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 511 A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 512 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 513 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 514 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 515 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 516 A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 517 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 518 A6XX_PROTECT_RDONLY(0x501, 0xa)); 519 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 520 A6XX_PROTECT_RDONLY(0x511, 0x44)); 521 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 522 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 523 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 524 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 525 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 526 A6XX_PROTECT_RW(0xbe20, 0x11f3)); 527 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 528 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 529 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 530 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 531 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 532 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 533 A6XX_PROTECT_RDONLY(0x980, 0x4)); 534 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 535 536 if (adreno_is_a650(adreno_gpu)) { 537 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 538 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 539 } 540 541 /* Enable interrupts */ 542 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 543 544 ret = adreno_hw_init(gpu); 545 if (ret) 546 goto out; 547 548 ret = a6xx_ucode_init(gpu); 549 if (ret) 550 goto out; 551 552 /* Always come up on rb 0 */ 553 a6xx_gpu->cur_ring = gpu->rb[0]; 554 555 /* Enable the SQE_to start the CP engine */ 556 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 557 558 ret = a6xx_cp_init(gpu); 559 if (ret) 560 goto out; 561 562 /* 563 * Try to load a zap shader into the secure world. If successful 564 * we can use the CP to switch out of secure mode. If not then we 565 * have no resource but to try to switch ourselves out manually. If we 566 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 567 * be blocked and a permissions violation will soon follow. 568 */ 569 ret = a6xx_zap_shader_init(gpu); 570 if (!ret) { 571 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 572 OUT_RING(gpu->rb[0], 0x00000000); 573 574 a6xx_flush(gpu, gpu->rb[0]); 575 if (!a6xx_idle(gpu, gpu->rb[0])) 576 return -EINVAL; 577 } else if (ret == -ENODEV) { 578 /* 579 * This device does not use zap shader (but print a warning 580 * just in case someone got their dt wrong.. hopefully they 581 * have a debug UART to realize the error of their ways... 582 * if you mess this up you are about to crash horribly) 583 */ 584 dev_warn_once(gpu->dev->dev, 585 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 586 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 587 ret = 0; 588 } else { 589 return ret; 590 } 591 592 out: 593 /* 594 * Tell the GMU that we are done touching the GPU and it can start power 595 * management 596 */ 597 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 598 599 /* Take the GMU out of its special boot mode */ 600 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 601 602 return ret; 603 } 604 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org